Δt
參數(shù)資料
型號(hào)： AD9522-1/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 41/84頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9522-1 CLK GEN
設(shè)計(jì)資源： AD9522 Eval Board Schematic
AD9522 BOM
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9522-1
主要屬性： 12 LVDS/24 CMOS 輸出，2.4 GHz VCO
次要屬性： I²C & SPI 接口
已供物品： 板
AD9522-1
Rev. 0 | Page 46 of 84
The RESET pin is forced low and then released (chip reset).
Let
Δt = delay (in seconds).
Δc = delay (in cycles of clock signal at input to DX).
TX = period of the clock signal at the input of the divider, DX (in
seconds).
Φ =
16 × SH[4] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] + 1 × PO[0]
The PD pin is forced low and then released (chip power-
down).
Whenever a VCO calibration is completed, an internal
SYNC signal is automatically asserted at the beginning and
released upon the completion of a VCO calibration.
The most common way to execute the SYNC function is to use
the SYNC pin to perform a manual synchronization of the outputs.
This requires a low going signal on the SYNC pin, which is held
low and then released when synchronization is desired. The
timing of the SYNC operation is shown in
(using the
VCO divider) and in
(the VCO divider is not used).
There is an uncertainty of up to one cycle of the clock at the
input to the channel divider due to the asynchronous nature of
the SYNC signal with respect to the clock edges inside the AD9522.
The channel divide-by is set as N = high cycles and M = low
cycles.
Case 1
For Φ ≤ 15,
Δt = Φ × TX
Δc = Δt/TX = Φ
Case 2
For Φ ≥ 16,
Δt = (Φ 16 + M + 1) × TX
Δc = Δt/TX
The pipeline delay from the SYNC rising edge to the beginning
of the synchronized output clocking is between 14 cycles and
15 cycles of clock at the channel divider input, plus one cycle of
the VCO divider input (see
) or one cycle of the
channel divider input (see
), depending on whether the
VCO divider is used. Cycles are counted from the rising edge of
the signal. In addition, there is an additional 1.2 ns (typical) delay
from the SYNC signal to the internal synchronization logic, as well
as the propagation delay of the output driver. The driver
propagation delay is approximately 100 ps for the LVDS driver
and approximately 1.5 ns for the CMOS driver.
By giving each divider a different phase offset, output-to-output
delays can be set in increments of the channel divider input
clock cycle. Figure 51 shows the results of setting such a coarse
offset between outputs.
0
1
2
3
4
5
6
7
8
9 1011121314 15
Tx
DIVIDER 0
DIVIDER 1
DIVIDER 2
CHANNEL
DIVIDER INPUT
SH = 0
PO = 0
SH = 0
PO = 1
SH = 0
PO = 2
1 × Tx
2 × Tx
CHANNEL DIVIDER OUTPUTS
DIV = 4, DUTY = 50%
07
220-
071
Another common way to execute the SYNC function is by
setting and resetting the soft SYNC bit at 0x230[0]. Both setting
and resetting of the soft SYNC bit require an update all registers
(0x232[0] = 1b) operation to take effect.
A SYNC operation brings all outputs that have not been excluded
(by the ignore SYNC bit) to a preset condition before allowing
the outputs to begin clocking in synchronicity. The preset condition
takes into account the settings in each of the channel’s start high
bit and its phase offset. These settings govern both the static state
of each output when the SYNC operation is happening and the
state and relative phase of the outputs when they begin clocking
again upon completion of the SYNC operation. A SYNC operation
must take place in order for the phase offsets setting to take effect.
Figure 51. Effect of Coarse Phase Offset (or Delay)
Synchronizing the Outputs—SYNC Function
The AD9522 clock outputs can be synchronized to each other.
Outputs can be individually excluded from synchronization.
Synchronization consists of setting the nonexcluded outputs to
a preset set of static conditions. These conditions include the
divider ratio and phase offsets for a given channel divider. This
allows the user to specify different divide ratios and phase offsets
for each of the four channel dividers. Releasing the SYNC pin
allows the outputs to continue clocking with the preset conditions
applied.
The AD9522 differential LVDS outputs are four groups of three,
sharing a channel divider per triplet. In the case of CMOS, each
LVDS differential pair can be configured as two single-ended
CMOS outputs. The synchronization conditions apply to all of
the drivers that belong to that channel divider.
Synchronization of the outputs is executed in the following ways:
The SYNC pin is forced low and then released (manual sync).
Each channel (a divider and its outputs) can be excluded from
any SYNC operation by setting the ignore SYNC bit of the channel.
Channels that are set to ignore SYNC (excluded channels) do
not set their outputs static during a SYNC operation, and their
outputs are not synchronized with those of the included channels.
By setting and then resetting any one of the following three
bits: the soft SYNC bit (0x230[0]), the soft reset bit
(0x000[5] [mirrored]), and the power-down distribution
reference bit (0x230[1]).
Synchronization of the outputs can be executed as part of
the chip power-up sequence.
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