Typical (typ) is given for VS = 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; T" />
參數(shù)資料
型號(hào)： AD9522-1/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 34/84頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9522-1 CLK GEN
設(shè)計(jì)資源： AD9522 Eval Board Schematic
AD9522 BOM
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9522-1
主要屬性： 12 LVDS/24 CMOS 輸出，2.4 GHz VCO
次要屬性： I²C & SPI 接口
已供物品： 板
AD9522-1
Rev. 0 | Page 4 of 84
SPECIFICATIONS
Typical (typ) is given for VS = 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ, unless otherwise noted. Minimum
(min) and maximum (max) values are given over full VS and TA (40°C to +85°C) variation.
POWER SUPPLY REQUIREMENTS
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
VS
3.135
3.3
3.465
V
3.3 V ± 5%
VCP
VS
5.25
V
This is nominally 3.3 V to 5.0 V ± 5%
RSET Pin Resistor
4.12
kΩ
Sets internal biasing currents; connect to ground
CPRSET Pin Resistor
5.1
kΩ
Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 μA);
actual current can be calculated by CP_lsb = 3.06/CPRSET; connect to ground
BYPASS Pin Capacitor
220
nF
Bypass for internal LDO regulator; necessary for LDO stability; connect to ground
PLL CHARACTERISTICS
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
VCO (ON-CHIP)
Frequency Range
2270
2650
MHz
VCO Gain (KVCO)
50
MHz/V
Tuning Voltage (VT)
0.5
VCP
0.5
V
VCP ≤ VS when using internal VCO
Frequency Pushing (Open-Loop)
1
MHz/V
Phase Noise @ 1 kHz Offset
62
dBc/Hz
LVDS output; fVCO = 2460 MHz; fOUT = 615 MHz
Phase Noise @ 100 kHz Offset
118
dBc/Hz
LVDS output; fVCO = 2460 MHz; fOUT = 615 MHz
Phase Noise @ 1 MHz Offset
136
dBc/Hz
LVDS output; fVCO = 2460 MHz; fOUT = 615 MHz
REFERENCE INPUTS
Differential Mode (REFIN, REFIN)
Differential mode (can accommodate single-ended
input by ac grounding undriven input)
Input Frequency
0
250
MHz
Frequencies below about 1 MHz should be dc-coupled;
be careful to match VCM (self-bias voltage)
Input Sensitivity
280
mV p-p
Self-Bias Voltage, REFIN
1.35
1.60
1.75
V
Self-bias voltage of REFIN1
Self-Bias Voltage, REFIN
1.30
1.50
1.60
V
Self-bias voltage of REFIN1
Input Resistance, REFIN
4.0
4.8
5.9
kΩ
Self-biased1
Input Resistance, REFIN
4.4
5.3
6.4
kΩ
Self-biased1
Dual Single-Ended Mode (REF1, REF2)
Two single-ended CMOS-compatible inputs
Input Frequency (AC-Coupled)
with DC Offset Off )
10
250
MHz
Slew rate must be > 50 V/μs
Input Frequency (AC-Coupled
with DC Offset On)
250
MHz
Slew rate must be > 50 V/μs, and input amplitude
sensitivity specification must be met; see input sensitivity
Input Frequency (DC-Coupled)
0
250
MHz
Slew rate > 50 V/μs; CMOS levels
Input Sensitivity (AC-Coupled
with DC Offset Off )
0.55
3.28
V p-p
VIH should not exceed VS
Input Sensitivity (AC-Coupled
with DC Offset On)
1.5
2.78
V p-p
VIH should not exceed VS
Input Logic High, DC Offset Off
2.0
V
Input Logic Low, DC Offset Off
0.8
V
Input Current
100
+100
μA
Input Capacitance
2
pF
Each pin, REFIN (REF1)/REFIN (REF2)
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