參數(shù)資料
型號： AD9522-1/PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 25/84頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9522-1 CLK GEN
設計資源： AD9522 Eval Board Schematic
AD9522 BOM
標準包裝： 1
主要目的： 計時，時鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9522-1
主要屬性： 12 LVDS/24 CMOS 輸出，2.4 GHz VCO
次要屬性： I²C & SPI 接口
已供物品： 板
AD9522-1
Rev. 0 | Page 31 of 84
Mode 2: High Frequency Clock Distribution—CLK or
External VCO > 1600 MHz
The AD9522 power-up default configuration has the PLL
powered off and the routing of the input set so that the CLK/
CLK input is connected to the distribution section through the
VCO divider (divide-by-1/divide-by-2/divide-by-3/divide-by-4/
divide-by-5/divide-by-6). This is a distribution-only mode that
allows for an external input up to 2400 MHz (see
). The
maximum frequency that can be applied to the channel dividers
is 1600 MHz; therefore, higher input frequencies must be divided
down before reaching the channel dividers.
When the PLL is enabled, this routing also allows the use of the
PLL with an external VCO or VCXO with a frequency <2400 MHz.
In this configuration, the internal VCO is not used and is powered
off. The external VCO/VCXO feeds directly into the prescaler.
The register settings shown in Table 26 are the default values of
these registers at power-up or after a reset operation.
Table 26. Default Register Settings for Clock Distribution Mode
Register
Description
0x010[1:0] = 01b
PLL asynchronous power-down (PLL off )
0x1E0[2:0] = 000b
Set VCO divider = 2
0x1E1[0] = 0b
Use the VCO divider
0x1E1[1] = 0b
CLK selected as the source
When using the internal PLL with an external VCO, the PLL
must be turned on.
Table 27. Settings When Using an External VCO
Register
Description
0x010[1:0] = 00b
PLL normal operation (PLL on)
0x010 to 0x01E
PLL settings; select and enable a
reference input; set R, N (P, A, B), PFD
polarity, and ICP according to the intended
loop configuration
0x1E1[1] = 0b
CLK selected as the source
An external VCO requires an external loop filter that must be
connected between CP and the tuning pin of the VCO. This
loop filter determines the loop bandwidth and stability of the
PLL. Make sure to select the proper PFD polarity for the VCO
being used.
Table 28. Setting the PFD Polarity
Register
Description
0x010[7] = 0b
PFD polarity positive (higher control
voltage produces higher frequency)
0x010[7] = 1b
PFD polarity negative (higher control
voltage produces lower frequency)
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AD9522-2BCPZ 功能描述:IC CLOCK GEN 2.2GHZ VCO 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:帶卷 (TR)
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