參數(shù)資料
型號(hào)： AD9516-5/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/76頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9516-5 2.5GHZ
產(chǎn)品培訓(xùn)模塊： Active Filter Design Tools
設(shè)計(jì)資源： AD9516 Eval Brd Schematic
AD9516 Gerber Files
AD9516-5 BOM
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9516-5
主要屬性： 2 輸入，14 輸出
次要屬性： CMOS、LVDS、LVPECL 輸出邏輯，ADIsimCLK&trade 圖形用戶界面
已供物品： 板，線纜，CD，電源
AD9516-5
Rev. A | Page 17 of 76
Pin No.
Input/
Output
Pin Type
Mnemonic
Description
16
I
3.3 V CMOS
SCLK
Serial Control Port Data Clock Signal.
17
I
3.3 V CMOS
CS
Serial Control Port Chip Select; Active Low. This pin has an internal 30 kΩ pull-up
resistor.
21
O
3.3 V CMOS
SDO
Serial Control Port Unidirectional Serial Data Output.
22
I/O
3.3 V CMOS
SDIO
Serial Control Port Bidirectional Serial Data Input/Output.
23
I
3.3 V CMOS
RESET
Chip Reset; Active Low. This pin has an internal 30 kΩ pull-up resistor.
24
I
3.3 V CMOS
PD
Chip Power-Down; Active Low. This pin has an internal 30 kΩ pull-up resistor.
25
O
LVPECL
OUT4
LVPECL Output; One Side of a Differential LVPECL Output.
26
O
LVPECL
OUT4
LVPECL Output; One Side of a Differential LVPECL Output.
27, 41, 54
I
Power
VS_LVPECL
Extended Voltage 2.5 V to 3.3 V LVPECL Power Pins.
28
O
LVPECL
OUT5
LVPECL Output; One Side of a Differential LVPECL Output.
29
O
LVPECL
OUT5
LVPECL Output; One Side of a Differential LVPECL Output.
33
O
LVDS or CMOS
OUT8 (OUT8A)
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended
CMOS Output.
34
O
LVDS or CMOS
OUT8 (OUT8B)
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended
CMOS Output.
O
LVDS or CMOS
OUT9 (OUT9A)
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended
CMOS Output.
36
O
LVDS or CMOS
OUT9 (OUT9B)
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended
CMOS Output.
37, 44, 59,
EPAD
I
GND
Ground Pins, Including External Paddle (EPAD). The external die paddle on the
bottom of the package must be connected to ground for proper operation.
39
O
LVPECL
OUT3
LVPECL Output; One Side of a Differential LVPECL Output.
40
O
LVPECL
OUT3
LVPECL Output; One Side of a Differential LVPECL Output.
42
O
LVPECL
OUT2
LVPECL Output; One Side of a Differential LVPECL Output.
43
O
LVPECL
OUT2
LVPECL Output; One Side of a Differential LVPECL Output.
45
O
LVDS or CMOS
OUT7 (OUT7B)
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended
CMOS Output.
46
O
LVDS or CMOS
OUT7 (OUT7A)
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended
CMOS Output.
47
O
LVDS or CMOS
OUT6 (OUT6B)
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended
CMOS Output.
48
O
LVDS or CMOS
OUT6 (OUT6A)
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended
CMOS Output.
52
O
LVPECL
OUT1
LVPECL Output; One Side of a Differential LVPECL Output.
53
O
LVPECL
OUT1
LVPECL Output; One Side of a Differential LVPECL Output.
55
O
LVPECL
OUT0
LVPECL Output; One Side of a Differential LVPECL Output.
56
O
LVPECL
OUT0
LVPECL Output; One Side of a Differential LVPECL Output.
58
O
Current set
resistor
RSET
A resistor connected to this pin sets internal bias currents. Nominal value = 4.12 kΩ.
62
O
Current set
resistor
CPRSET
A resistor connected to this pin sets the CP current range. Nominal value = 5.1 kΩ.
This resistor can be omitted if the PLL is not used.
63
I
Reference
input
REFIN (REF2)
Along with REFIN, this pin is the differential input for the PLL reference.
Alternatively, this pin is a single-ended input for REF2. This pin can be left
unconnected when the PLL is not used.
64
I
Reference
input
REFIN (REF1)
Along with REFIN, this pin is the differential input for the PLL reference.
Alternatively, this pin is a single-ended input for REF1. This pin can be left
unconnected when the PLL is not used.
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