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參數(shù)資料
| 型號(hào)： | AD9516-5/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/76頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9516-5 2.5GHZ |
| 產(chǎn)品培訓(xùn)模塊： | Active Filter Design Tools |
| 設(shè)計(jì)資源： | AD9516 Eval Brd Schematic AD9516 Gerber Files AD9516-5 BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9516-5 |
| 主要屬性： | 2 輸入，14 輸出 |
| 次要屬性： | CMOS、LVDS、LVPECL 輸出邏輯，ADIsimCLK&trade 圖形用戶界面 |
| 已供物品： | 板，線纜，CD，電源 |
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AD9516-5
Rev. A | Page 26 of 76
Table 19. Settings for Using an Internal PLL with an External
VCO < 1600 MHz
Register
Description
0x1E1[0] = 1b
Bypass the VCO divider as source for
distribution section
0x010[1:0] = 00b
PLL normal operation (PLL on) along with other
appropriate PLL settings in Register 0x010 to
Register 0x01E
An external VCO/VCXO requires an external loop filter that
must be connected between CP and the tuning pin of the VCO/
VCXO. This loop filter determines the loop bandwidth and
stability of the PLL. Ensure that the correct PFD polarity is
selected for the VCO/VCXO that is being used.
Table 20. Setting the PFD Polarity
Register
Description
0x010[7] = 0b
PFD polarity positive (higher control voltage
produces higher frequency)
0x010[7] = 1b
PFD polarity negative (higher control voltage
produces lower frequency)
After the appropriate register values are programmed,
Register 0x232 must be set to 0x01 for the values to take effect.
Mode 2 (High Frequency Clock Distribution)—CLK or
External VCO > 1600 MHz
The AD9516 power-up default configuration has the PLL
powered off and the routing of the input set so that the CLK/
CLK input is connected to the distribution section through the
VCO divider (divide-by-2/divide-by-3/divide-by-4/divide-by-5/
divide-by-6). This is a distribution-only mode that allows for an
external input of up to 2400 MHz (see Table 4). For divide ratios
other than 1, the maximum frequency that can be applied to the
channel dividers is 1600 MHz. Therefore, the VCO divider must
be used to divide down input frequencies that are greater than
1600 MHz before the channel dividers can be used for further
division. This input routing can also be used for lower input
frequencies, but the minimum divide is 2 before the channel
dividers.
When the PLL is enabled, this routing also allows the use of
the PLL with an external VCO or VCXO with a frequency of
<2400 MHz. In this configuration, the external VCO/VCXO
feeds directly into the prescaler.
The register settings shown in Table 21 are the default values
of these registers at power-up or after a reset operation. If the
contents of the registers are altered by prior programming after
power-up or reset, these registers can also be set intentionally to
these values.
Table 21. Default Settings of Some PLL Registers
Register
Description
0x010[1:0] = 01b
PLL asynchronous power-down (PLL off ).
0x1E0[2:0] = 010b
Set VCO divider = 4.
0x1E1[0] = 0b
Use the VCO divider.
When using the internal PLL with an external VCO, the PLL
must be turned on.
Table 22. Settings When Using an External VCO
Register
Description
0x010[1:0] = 00b
PLL normal operation (PLL on).
0x010 to 0x01D
PLL settings. Select and enable a reference
input. Set R, N (P, A, B), PFD polarity, and ICP
according to the intended loop configuration.
0x1E1[1] = 0b
CLK selected as the source.
An external VCO requires an external loop filter that must be
connected between CP and the tuning pin of the VCO. This loop
filter determines the loop bandwidth and stability of the PLL.
Ensure that the correct PFD polarity is selected for the VCO
that is being used.
Table 23. Setting the PFD Polarity
Register
Description
0x010[7] = 0b
PFD polarity positive (higher control
voltage produces higher frequency).
0x010[7] = 1b
PFD polarity negative (higher control
voltage produces lower frequency).
After the appropriate register values are programmed,
Register 0x232 must be set to 0x01 for the values to take effect.
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