參數(shù)資料
型號(hào)： AD9516-5/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 52/76頁(yè)
文件大小： 0K
描述： BOARD EVAL FOR AD9516-5 2.5GHZ
產(chǎn)品培訓(xùn)模塊： Active Filter Design Tools
設(shè)計(jì)資源： AD9516 Eval Brd Schematic
AD9516 Gerber Files
AD9516-5 BOM
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9516-5
主要屬性： 2 輸入，14 輸出
次要屬性： CMOS、LVDS、LVPECL 輸出邏輯，ADIsimCLK&trade 圖形用戶界面
已供物品： 板，線纜，CD，電源
AD9516-5
Rev. A | Page 56 of 76
Reg.
Addr.
(Hex)
Bits
Name
Description
0x01A
6
Reference
frequency
monitor
threshold
Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect the CLK
frequency monitor’s detection threshold (see Table 12: REF1, REF2, and CLK frequency status monitor parameter).
0: frequency valid if frequency is above the higher frequency threshold (default).
1: frequency valid if frequency is above the lower frequency threshold.
[5:0]
LD pin control
Selects the LD pin signal.
5
4
3
2
1
0
Level or
Dynamic
Signal
Signal at LD Pin
0
LVL
Digital lock detect (high = lock, low = unlock) (default)
0
1
DYN
P-channel, open-drain lock detect (analog lock detect)
0
1
0
DYN
N-channel, open-drain lock detect (analog lock detect)
0
1
HIZ
High-Z LD pin
0
1
0
CUR
Current source lock detect (110 μA when DLD is true)
0
X
LVL
Ground (dc); for all other cases of 0x0XXXX not specified
The selections that follow are the same as for REFMON:
1
0
LVL
Ground (dc)
1
0
1
DYN
REF1 clock (differential reference when in differential mode)
1
0
1
0
DYN
REF2 clock (not available in differential mode)
1
0
1
DYN
Selected reference to PLL (differential reference when in differential mode)
1
0
1
0
DYN
Unselected reference to PLL (not available in differential mode)
1
0
1
0
1
LVL
Status of selected reference (status of differential reference); active high
1
0
1
0
LVL
Status of unselected reference (not available in differential mode); active high
1
0
1
LVL
Status of REF1 frequency (active high)
1
0
1
0
LVL
Status of REF2 frequency (active high)
1
0
1
0
1
LVL
(Status of REF1 frequency) AND (status of REF2 frequency)
1
0
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of CLK)
1
0
1
0
1
LVL
Status of CLK frequency (active high)
1
0
1
0
LVL
Selected reference (low = REF1, high = REF2)
1
0
1
0
1
LVL
Digital lock detect (DLD); active high
1
0
1
0
LVL
Holdover active (active high)
1
0
1
LVL
Not available; do not use
1
0
LVL
VS (PLL supply)
1
0
1
DYN
REF1 clock (differential reference when in differential mode)
1
0
1
0
DYN
REF2 clock (not available in differential mode)
1
0
1
DYN
Selected reference to PLL (differential reference when in differential mode)
1
0
1
0
DYN
Unselected reference to PLL (not available when in differential mode)
1
0
1
0
1
LVL
Status of selected reference (status of differential reference); active low
1
0
1
0
LVL
Status of unselected reference (not available in differential mode); active low
1
0
1
LVL
Status of REF1 frequency (active low)
1
0
LVL
Status of REF2 frequency (active low)
1
0
1
LVL
(Status of REF1 frequency) AND (status of REF2 frequency)
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of CLK)
1
0
1
LVL
Status of CLK frequency (active low)
1
0
LVL
Selected reference (low = REF2, high = REF1)
1
0
1
LVL
Digital lock detect (DLD); active low
1
0
LVL
Holdover active (active low)
1
LVL
Not available; do not use
0x01B
7
CLK frequency
monitor
Enables or disables CLK frequency monitor.
0: disables CLK frequency monitor (default).
1: enables CLK frequency monitor.
6
REF2 (REFIN)
frequency
monitor
Enables or disables REF2 frequency monitor.
0: disables REF2 frequency monitor (default).
1: enables REF2 frequency monitor.
5
REF1 (REFIN)
frequency
monitor
REF1 (REFIN) frequency monitor enable; this is for both REF1 (single-ended) and REFIN (differential) inputs (as selected
by differential reference mode).
0: disables REF1 (REFIN) frequency monitor (default).
1: enables REF1 (REFIN) frequency monitor.
相關(guān)PDF資料
PDF描述
FCBP110LD1L05 CABLE 10.5GBPS 5M LASERWIRE
VE-JTV-EZ-S CONVERTER MOD DC/DC 5.8V 25W
AD9522-2/PCBZ BOARD EVAL FOR AD9522-2 CLK GEN
FCBP110LD1L03 CABLE 10.5GBPS 3M LASERWIRE
MCP121T-240E/TT IC SUPERVISOR 2.32V LOW SOT-23B
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9517-0A/PCBZ 功能描述:BOARD EVALUATION FOR AD9517-0A RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081
AD9517-0ABCPZ 功能描述:IC CLOCK GEN 2.8GHZ VCO 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無(wú) 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND
AD9517-0ABCPZ-RL7 功能描述:IC CLOCK GEN 2.8GHZ VCO 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大:240MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR)
AD9517-0BCPZ 制造商:Analog Devices 功能描述:
AD9517-1 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Output Clock Generator with Integrated 2.5 GHz VCO
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*