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參數(shù)資料
| 型號： | AD9516-5/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 63/76頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9516-5 2.5GHZ |
| 產(chǎn)品培訓(xùn)模塊： | Active Filter Design Tools |
| 設(shè)計(jì)資源： | AD9516 Eval Brd Schematic AD9516 Gerber Files AD9516-5 BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9516-5 |
| 主要屬性： | 2 輸入，14 輸出 |
| 次要屬性： | CMOS、LVDS、LVPECL 輸出邏輯，ADIsimCLK&trade 圖形用戶界面 |
| 已供物品： | 板，線纜，CD，電源 |
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AD9516-5
Rev. A | Page 66 of 76
Reg.
Addr.
(Hex)
Bits
Name
Description
[2:1]
OUT9 LVDS output current
Sets output current level in LVDS mode. This has no effect in CMOS mode.
2
1
Current (mA)
Recommended Termination (Ω)
0
1.75
100
0
1
3.5
100 (default)
1
0
5.25
50
1
7
50
[0]
OUT9 power-down
Power-down output (LVDS/CMOS).
0: powers on.
1: powers off (default).
Table 53. LVPECL Channel Dividers
Reg.
Addr.
(Hex)
Bits
Name
Description
0x190
[7:4]
Divider 0 low cycles
Number of clock cycles (minus 1) of the Divider 0 input during which the Divider 0 output
stays low. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0).
[3:0]
Divider 0 high cycles
Number of clock cycles (minus 1) of the Divider 0 input during which the Divider 0 output
stays high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0).
0x191
7
Divider 0 bypass
Bypasses and powers down the divider; routes input to the divider output.
0: uses the divider.
1: bypasses the divider (default).
6
Divider 0 nosync
No sync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
5
Divider 0 force high
Forces divider output to high. This operation requires that the Divider 0 nosync bit (Bit 6) also
be set. This bit has no effect if the Divider 0 bypass bit (Bit 7) is set.
0: normal operation (default).
1: divider output forced to the setting of the Divider 0 start high bit.
4
Divider 0 start high
Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
[3:0]
Divider 0 phase offset
Phase offset (default: 0x0).
0x192
1
Divider 0 direct to output
Connects OUT0 and OUT1 to Divider 0 or directly to CLK input.
0: OUT0 and OUT1 are connected to Divider 0 (default).
1: If Register 0x1E1[0] = 0b, the CLK is routed directly to OUT0 and OUT1.
If Register 0x1E1[0] = 1b, there is no effect.
0
Divider 0 DCCOFF
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
0x193
[7:4]
Divider 1 low cycles
Number of clock cycles (minus 1) of the Divider 1 input during which the Divider 1 output stays
low. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0xB).
[3:0]
Divider 1 high cycles
Number of clock cycles (minus 1) of the Divider 1 input during which the Divider 1 output stays
high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0xB).
0x194
7
Divider 1 bypass
Bypasses and powers down the divider; routes input to divider output.
0: uses divider (default).
1: bypasses divider.
6
Divider 1 nosync
No sync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
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| AD9517-0A/PCBZ | 功能描述:BOARD EVALUATION FOR AD9517-0A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| AD9517-0ABCPZ | 功能描述:IC CLOCK GEN 2.8GHZ VCO 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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| AD9517-0BCPZ | 制造商:Analog Devices 功能描述: |
| AD9517-1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Output Clock Generator with Integrated 2.5 GHz VCO |
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