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| 型號： | AD9516-5/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 32/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9516-5 2.5GHZ |
| 產品培訓模塊： | Active Filter Design Tools |
| 設計資源： | AD9516 Eval Brd Schematic AD9516 Gerber Files AD9516-5 BOM |
| 標準包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9516-5 |
| 主要屬性： | 2 輸入，14 輸出 |
| 次要屬性： | CMOS、LVDS、LVPECL 輸出邏輯，ADIsimCLK&trade 圖形用戶界面 |
| 已供物品： | 板，線纜，CD，電源 |
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AD9516-5
Rev. A | Page 38 of 76
Channel Frequency Division (Divider 3 and Divider 4)
The division for each channel divider is set by the bits in the
registers for the individual dividers (X.Y = 3.1, 3.2, 4.1, and 4.2).
Number of Low Cycles = MX.Y + 1
Number of High Cycles = NX.Y + 1
When both X.1 and X.2 are bypassed, DX = 1 × 1 = 1.
When only X.2 is bypassed, DX = (NX.1 + MX.1 + 2) × 1.
When both X.1 and X.2 are not bypassed, DX = (NX.1 + MX.1 + 2) ×
(NX.2 + MX.2 + 2).
By cascading the dividers, channel division up to 1024 can be
obtained. However, not all integer value divisions from 1 to
1024 are obtainable; only the values that are the product of the
separate divisions of the two dividers (DX.1 × DX.2) can be realized.
If only one divider is needed when using Divider 3 and Divider 4,
use the first one (X.1) and bypass the second one (X.2). Do not
bypass X.1 and use X.2.
Duty Cycle and Duty-Cycle Correction (Divider 3 and
Divider 4)
The same duty cycle and DCC considerations apply to Divider 3
and Divider 4 as to Divider 0, Divider 1, and Divider 2 (see the
however, with these channel dividers, the number of possible
configurations is more complex.
Duty-cycle correction on Divider 3 and Divider 4 requires the
following channel divider conditions:
An even DX.Y must be set as MX.Y = NX.Y (low cycles = high
cycles).
An odd DX.Y must be set as MX.Y = NX.Y + 1 (number of low
cycles must be one greater than the number of high cycles).
If only one divider is bypassed, it must be the second
divider, X.2.
If only one divider has an even divide-by, it must be the
second divider, X.2.
The possibilities for the duty cycle of the output clock from
Table 35. Divider 3 and Divider 4 Duty Cycle; VCO Divider
Used; Duty Cycle Correction Off (DCCOFF = 1)
DX.1
DX.2
VCO
Divider
NX.1 + MX.1 + 2
NX.2 + MX.2 + 2
Output Duty Cycle
Even
Bypassed
50%
Odd = 3
Bypassed
33.3%
Odd = 5
Bypassed
40%
Even
Even, odd
Bypassed
(NX.1 + 1)/
(NX.1 + MX.1 + 2)
Odd
Even, odd
Bypassed
(NX.1 + 1)/
(NX.1 + MX.1 + 2)
Even
Even, odd
(NX.2 + 1)/
(NX.2 + MX.2 + 2)
Odd
Even, odd
(NX.2 + 1)/
(NX.2 + MX.2 + 2)
Table 36. Divider 3 and Divider 4 Duty Cycle; VCO Divider
Not Used; Duty Cycle Correction Off (DCCOFF = 1)
DX.1
DX.2
Input
Clock
Duty
Cycle
NX.1 + MX.1 + 2
NX.2 + MX.2 + 2
Output
Duty Cycle
50%
Bypassed
50%
X%
Bypassed
X%
50%
Even, odd
Bypassed
(NX.1 + 1)/
(NX.1 + MX.1 + 2)
X%
Even, odd
Bypassed
(NX.1 + 1)/
(NX.1 + MX.1 + 2)
50%
Even, odd
(NX.2 + 1)/
(NX.2 + MX.2 + 2)
X%
Even, odd
(NX.2 + 1)/
(NX.2 + MX.2 + 2)
Table 37. Divider 3 and Divider 4 Duty Cycle; VCO Divider
Used; Duty Cycle Correction On (DCCOFF = 0); VCO Divider
Input Duty Cycle = 50%
DX.1
DX.2
VCO
Divider
NX.1 + MX.1 + 2
NX.2 + MX.2 + 2
Output
Duty Cycle
Even
Bypassed
50%
Odd
Bypassed
50%
Even
Even (NX.1 = MX.1)
Bypassed
50%
Odd
Even (NX.1 = MX.1)
Bypassed
50%
Even
Odd (MX.1 = NX.1 + 1)
Bypassed
50%
Odd
Odd (MX.1 = NX.1 + 1)
Bypassed
50%
Even
Even (NX.1 = MX.1)
Even
(NX.2 = MX.2)
50%
Odd
Even (NX.1 = MX.1)
Even
(NX.2 = MX.2)
50%
Even
Odd (MX.1 = NX.1 + 1)
Even
(NX.2 = MX.2)
50%
Odd
Odd (MX.1 = NX.1 + 1)
Even
(NX.2 = MX.2)
50%
Even
Odd (MX.1 = NX.1 + 1)
Odd
(MX.2 = NX.2 + 1)
50%
Odd
Odd (MX.1 = NX.1 + 1)
Odd
(MX.2 = NX.2 + 1)
50%
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