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參數(shù)資料
| 型號： | AD9516-5/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 28/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9516-5 2.5GHZ |
| 產(chǎn)品培訓(xùn)模塊： | Active Filter Design Tools |
| 設(shè)計資源： | AD9516 Eval Brd Schematic AD9516 Gerber Files AD9516-5 BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9516-5 |
| 主要屬性： | 2 輸入，14 輸出 |
| 次要屬性： | CMOS、LVDS、LVPECL 輸出邏輯，ADIsimCLK&trade 圖形用戶界面 |
| 已供物品： | 板，線纜，CD，電源 |
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AD9516-5
Rev. A | Page 34 of 76
The following registers affect the internal/automatic holdover
function:
Register 0x018[3] = 0b; DLD normal operation.
Register 0x01A[5:0] = 000100b; current source lock detect
mode.
Register 0x018[6:5], lock detect counter. These bits change
how many PFD cycles with edges inside the lock detect
window are required for the DLD indicator to indicate lock.
This impacts the time required before the LD pin can begin
to charge, as well as the delay from the end of a holdover
event until the holdover function can be reengaged.
Register 0x01B[7:0] = 0xF7; set REFMON pin to status of
REF1 (active low).
Register 0x01C[2:1] = 11b; enable REF1 and REF2 input
buffers.
Register 0x01D[3] = 1b; enable LD pin comparator.
Register 0x01D[2] = 1b; enable holdover function.
Register 0x018[3], disable digital lock detect. This bit must
be set to 0b to enable the DLD circuit. Internal/automatic
holdover does not operate correctly without the DLD function
enabled.
Register 0x01D[1] = 0b; use internal/automatic holdover
mode.
Register 0x01D[0] = 1b; enable holdover function
(complete VCO calibration before enabling this bit).
Register 0x01A[5:0], lock detect pin output select. Set this
to 000100b to put it in the current source lock detect mode
if using the LD pin comparator. Load the LD pin with a
capacitor of an appropriate value.
Register 0x232 = 0x01; update all registers.
And, finally,
Connect REFMON pin to REFSEL pin.
Register 0x01D[3], LD pin comparator enable. 1b = enable;
0b = disable. When disabled, the holdover function always
senses the LD pin as high.
Frequency Status Monitors
The AD9516 contains three frequency status monitors that are
used to indicate if the PLL reference (or references, in the case
of single-ended mode) and the VCO have fallen below a threshold
frequency. Figure 42 is a diagram that shows their location in
the PLL.
Register 0x01D[1], external holdover control.
Register 0x01D[0] and Register 0x01D[2], holdover enable.
If holdover is disabled, both external and automatic/internal
holdover are disabled.
For example, to use automatic holdover with the following:
The PLL reference frequency monitors have two threshold
frequencies: normal and extended (see Table 12). The reference
frequency monitor thresholds are selected in Register 0x01B[7:5].
The reference frequency monitor status can be found in
Register 0x01F[3:1].
Digital lock detect: five PFD cycles, high range window
Automatic holdover using the LD pin comparator
Set the following registers (in addition to the normal PLL registers):
Register 0x018[6:5] = 00b; lock detect counter = five cycles.
Register 0x018[4] = 0b; lock detect window = high range.
PROGRAMMABLE
N DELAY
REFIN (REF1)
REFIN (REF2)
CLK
REF1
REF2
STATUS
R
DIVIDER
PROGRAMMABLE
R DELAY
REFERENCE
SWITCHOVER
REF_SEL
CPRSET VCP
VS
GND
RSET
DISTRIBUTION
REFERENCE
REFMON
CP
STATUS
LD
P, P + 1
PRESCALER
A/B
COUNTERS
N DIVIDER
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
CHARGE
PUMP
PL
L
RE
F
E
RE
NCE
HOLD
0
1
0
1
DIVIDE BY
2, 3, 4, 5, OR 6
07
97
2-
0
70
CLK FREQUENCY
STATUS
Figure 42. Reference and CLK Status Monitors
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