參數(shù)資料
型號: AD9516-5/PCBZ
廠商: Analog Devices Inc
文件頁數(shù): 33/76頁
文件大小: 0K
描述: BOARD EVAL FOR AD9516-5 2.5GHZ
產(chǎn)品培訓(xùn)模塊: Active Filter Design Tools
設(shè)計資源: AD9516 Eval Brd Schematic
AD9516 Gerber Files
AD9516-5 BOM
標(biāo)準(zhǔn)包裝: 1
主要目的: 計時,時鐘發(fā)生器
嵌入式:
已用 IC / 零件: AD9516-5
主要屬性: 2 輸入,14 輸出
次要屬性: CMOS、LVDS、LVPECL 輸出邏輯,ADIsimCLK&trade 圖形用戶界面
已供物品: 板,線纜,CD,電源
AD9516-5
Rev. A | Page 39 of 76
Table 38. Divider 3 and Divider 4 Duty Cycle; VCO Divider
Used; Duty Cycle Correction On (DCCOFF = 0); VCO
Divider Input Duty Cycle = X%
DX.1
DX.2
VCO
Divider
NX.1 + MX.1 + 2
NX.2 + MX.2 +
2
Output
Duty Cycle
Even
Bypassed
50%
Odd = 3
Bypassed
(1 + X%)/3
Odd = 5
Bypassed
(2 + X%)/5
Even
(NX.1 = MX.1)
Bypassed
50%
Odd
Even
(NX.1 = MX.1)
Bypassed
50%
Even
Odd
(MX.1 = NX.1 + 1)
Bypassed
50%
Odd = 3
Odd
(MX.1 = NX.1 + 1)
Bypassed
(3NX.1 + 4 + X%)/
(6NX.1 + 9)
Odd = 5
Odd
(MX.1 = NX.1 + 1)
Bypassed
(5NX.1 + 7 + X%)/
(10NX.1 + 15)
Even
(NX.1 = MX.1)
Even
(NX.2 = MX.2)
50%
Odd
Even
(NX.1 = MX.1)
Even
(NX.2 = MX.2)
50%
Even
Odd
(MX.1 = NX.1 + 1)
Even
(NX.2 = MX.2)
50%
Odd
(MX.1 = NX.1 + 1)
Even
(NX.2 = MX.2)
50%
Even
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.2 = NX.2 + 1)
50%
Odd = 3
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.2 = NX.2 + 1)
(6NX.1NX.2 + 9NX.1 +
9NX.2 + 13 + X%)/
(3(2NX.1 + 3)
(2NX.2 + 3))
Odd = 5
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.2 = NX.2 + 1)
(10NX.1NX.2 + 15NX.1 +
15NX.2 + 22 + X%)/
(5(2 NX.1 + 3)
(2 NX.2 + 3))
Table 39. Divider 3 and Divider 4 Duty Cycle; VCO Divider
Not Used; Duty Cycle Correction On (DCCOFF = 0)
DX.1
DX.2
Input
Clock
Duty
Cycle
NX.1 + MX.1 + 2
NX.2 + MX.2 + 2
Output
Duty Cycle
50%
Bypassed
50%
Even
(NX.1 = MX.1)
Bypassed
50%
X%
Bypassed
X% (high)
X%
Even
(NX.1 = MX.1)
Bypassed
50%
Odd
(MX.1 = NX.1 + 1)
Bypassed
50%
Odd
(MX.1 = NX.1 + 1)
Bypassed
(NX.1 + 1 + X%)/
(2NX.1 + 3)
X%
Odd
(MX.1 = NX.1 + 1)
Bypassed
(NX.1 + 1 + X%)/
(2NX.1 + 3)
50%
Even
(NX.1 = MX.1)
Even
(NX.2 = MX.2)
50%
X%
Even
(NX.1 = MX.1)
Even
(NX.2 = MX.2)
50%
Odd
(MX.1 = NX.1 + 1)
Even
(NX.2 = MX.2)
50%
X%
Odd
(MX.1 = NX.1 + 1)
Even
(NX.2 = MX.2)
50%
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.2 = NX.2 + 1)
50%
X%
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.2 = NX.2 + 1)
(2NX.1NX.2 + 3NX.1 +
3NX.2 + 4 + X%)/
((2NX.1 + 3)(2NX.2 + 3))
Phase Offset or Coarse Time Delay (Divider 3 and Divider 4)
Divider 3 and Divider 4 can be set to have a phase offset or
delay. The phase offset is set by a combination of the bits in the
phase offset and start high registers (see Table 40).
Table 40. Setting Phase Offset and Division for Divider 3 and
Divider 41
Divider
Start
High (SH)
Phase
Offset (PO)
Low
Cycles M
High
Cycles N
3
3.1
0x19C[0]
0x19A[3:0]
0x199[7:4]
0x199[3:0]
3.2
0x19C[1]
0x19A[7:4]
0x19B[7:4]
0x19B[3:0]
4
4.1
0x1A1[0]
0x19F[3:0]
0x19E[7:4]
0x19E[3:0]
4.2
0x1A1[1]
0x19F[7:4]
0x1A0[7:4]
0x1A0[3:0]
1 Note that the value stored in the register is equal to the number of cycles
minus 1. For example, Register 0x199[7:4] = 0001b equals two low cycles
(M = 2) for Divider 3.1.
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