參數(shù)資料
型號: AD9516-5/PCBZ
廠商: Analog Devices Inc
文件頁數(shù): 56/76頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD9516-5 2.5GHZ
產(chǎn)品培訓模塊: Active Filter Design Tools
設計資源: AD9516 Eval Brd Schematic
AD9516 Gerber Files
AD9516-5 BOM
標準包裝: 1
主要目的: 計時,時鐘發(fā)生器
嵌入式:
已用 IC / 零件: AD9516-5
主要屬性: 2 輸入,14 輸出
次要屬性: CMOS、LVDS、LVPECL 輸出邏輯,ADIsimCLK&trade 圖形用戶界面
已供物品: 板,線纜,CD,電源
AD9516-5
Rev. A | Page 6 of 76
CLOCK INPUTS
Table 3.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CLOCK INPUTS (CLK, CLK)
Differential input
Input Frequency
2.4
GHz
High frequency distribution (VCO divider enabled)
1.6
GHz
Distribution only (VCO divider bypassed; this is the
frequency range supported by the channel divider)
Input Sensitivity, Differential
150
mV p-p
Measured at 2.4 GHz; jitter performance is
improved with slew rates > 1 V/ns
Input Level, Differential
2
V p-p
Larger voltage swings may turn on the
protection diodes and may degrade jitter
performance
Input Common-Mode Voltage, VCM
1.3
1.57
1.8
V
Self-biased; enables ac coupling
Input Common-Mode Range, VCMR
1.3
1.8
V
With 200 mV p-p signal applied; dc-coupled
Input Sensitivity, Single-Ended
150
mV p-p
CLK ac-coupled; CLK ac-bypassed to RF ground
Input Resistance
3.9
4.7
5.7
Self-biased
Input Capacitance
2
pF
1 Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM.
CLOCK OUTPUTS
Table 4.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL CLOCK OUTPUTS
Termination = 50 Ω to VS_LVPECL 2 V
OUT0, OUT1, OUT2, OUT3, OUT4,
OUT5
Differential (OUT, OUT)
Output Frequency, Maximum
2400
MHz
Using direct to output; see Figure 20 for peak-to-
peak differential amplitude
Output High Voltage (VOH)
VS_LVPECL 1.12
VS_LVPECL 0.98
VS_LVPECL 0.84
V
Measured at dc using the default amplitude setting;
see Figure 20 for amplitude vs. frequency
Output Low Voltage (VOL)
VS_LVPECL 2.03
VS_LVPECL 1.77
VS_LVPECL 1.49
V
Measured at dc using the default amplitude setting;
see Figure 20 for amplitude vs. frequency
Output Differential Voltage (VOD)
550
790
980
mV
VOH VOL for each leg of a differential pair for
default amplitude setting with driver not toggling;
see Figure 20 for variation over frequency
LVDS CLOCK OUTPUTS
Differential termination 100 Ω at 3.5 mA
OUT6, OUT7, OUT8, OUT9
Differential (OUT, OUT)
Output Frequency, Maximum
800
MHz
The AD9516 outputs can toggle at higher
frequencies, but the output amplitude may not
meet the VOD specification; see Figure 21
Differential Output Voltage (VOD)
247
360
454
mV
VOH VOL measurement across a differential pair
at the default amplitude setting with output
driver not toggling; see Figure 21 for variation
over frequency
Delta VOD
25
mV
This is the absolute value of the difference between
VOD when the normal output is high vs. when the
complementary output is high
Output Offset Voltage (VOS)
1.125
1.24
1.375
V
(VOH + VOL)/2 across a differential pair at the
default amplitude setting with output driver not
toggling
Delta VOS
25
mV
This is the absolute value of the difference between
VOS when the normal output is high vs. when the
complementary output is high
Short-Circuit Current (ISA, ISB)
14
24
mA
Output shorted to GND
CMOS CLOCK OUTPUTS
OUT6A, OUT6B, OUT7A, OUT7B,
OUT8A, OUT8B, OUT9A, OUT9B
Single-ended; termination = 10 pF
Output Frequency
250
MHz
Output Voltage High (VOH)
VS_LVPECL 0.1
V
At 1 mA load
Output Voltage Low (VOL)
0.1
V
At 1 mA load
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