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參數(shù)資料
| 型號： | AD73360LAR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Six-Input Channel Analog Front End |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 9/32頁 |
| 文件大?。?/td> | 287K |
| 代理商： | AD73360LAR |
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REV. 0
AD73360L
–9–
Figure 7 shows the various stages of filtering that are employed
in a typical AD73360L application. In Figure 7a we see the trans-
fer function of the external analog antialias filter. Even though it
is a single RC pole, its cutoff frequency is sufficiently far away
from the initial sampling frequency (DMCLK/8) that it takes care
of any signals that could be aliased by the sampling frequency.
This also shows the major difference between the initial oversam-
pling rate and the bandwidth of interest. In Figure 7b, the signal
and noise-shaping responses of the sigma-delta modulator are
shown. The signal response provides further rejection of any
high-frequency signals while the noise-shaping will push the
inherent quantization noise to an out-of-band position. The detail
of Figure 7c shows the response of the digital decimation filter
(sinc-cubed response) with nulls every multiple of DMCLK/
256, which is the decimation filter update rate. The final detail
in Figure 7d shows the application of a final antialias filter in the
DSP engine. This has the advantage of being implemented accord-
ing to the user
’
s requirements and available MIPS. The filtering in
Figures 7a through 7c is implemented in the AD73360L.
F
B
= 4kHz
F
SINIT
= DMCLK/8
a. Analog Antialias Filter Transfer Function
F
B
= 4kHz
F
SINIT
= DMCLK/8
NOISE TRANSFER FUNCTION
SIGNAL TRANSFER FUNCTION
b. Analog Sigma-Delta Modulator Transfer Function
F
B
= 4kHz
F
SINTER
= DMCLK/256
c. Digital Decimator Transfer Function
F
B
= 4kHz
F
SINTER
= DMCLK/256
F
SFINAL
= 8kHz
d. Final Filter LPF (HPF) Transfer Function
Figure 7. DC Frequency Responses
Decimation Filter
The digital filter used in the AD73360L carries out two impor-
tant functions. Firstly, it removes the out-of-band quantization
noise, which is shaped by the analog modulator and secondly, it
decimates the high-frequency bitstream to a lower rate 15-bit word.
The antialiasing decimation filter is a sinc-cubed digital filter
that reduces the sampling rate from DMCLK/8 to DMCLK/
256, and increases the resolution from a single bit to 15 bits. Its
Z transform is given as: [(1
–
Z
–
32
)/(1
–
Z
–
1
)]
3
. This ensures a mini-
mal group delay of 25
μ
s.
Word growth in the decimator is determined by the sampling
rate. At 64 kHz sampling, where the oversampling ratio between
the sigma-delta modulator and decimator output equals 32,
there are five bits per stage of the three-stage Sinc
3
filter. Due to
symmetry within the sigma-delta modulator, the LSB will always
be a zero; therefore, the 16-bit ADC output word will have
2 LSBs equal to zero, one due to the sigma-delta symmetry and
the other being a padded zero to make up a 16-bit word. At
lower sampling rates, decimator word growth will be greater
than the 16-bit sample word, therefore truncation occurs in trans-
ferring the decimator output as the ADC word. For example
at 8 kHz sampling, word growth reaches 24 bits due to the OSR
of 256 between sigma-delta modulator and decimator. This yields
eight bits per stage of the three stage Sinc
3
filter.
ADC Coding
The ADC coding scheme is in two
’
s complement format (see
Figure 8). The output words are formed by the decimation
filter, which grows the word length from the single-bit output of
the sigma-delta modulator to a 15-bit word, which is the final
output of the ADC block. In 16-bit Data Mode this value is left
shifted with the LSB being set to 0. For input values equal to or
greater than positive full scale, however, the output word is set
at 0x7FFF, which has the LSB set to 1. In mixed Control/Data
Mode, the resolution is fixed at 15 bits, with the MSB of the
16-bit transfer being used as a flag bit to indicate either control
or data in the frame.
V
REF
+ (V
REF
0.32875)
V
REF
V
REF
–
(V
REF
0.32875)
10...00
00...00
01...11
ADC CODE DIFFERENTIAL
ANALOG
INPUT
V
INN
V
INP
V
REF
+ (V
REF
0.6575)
V
REF
–
(V
REF
0.6575)
10...00
00...00
01...11
ADC CODE SINGLE-ENDED
ANALOG
INPUT
V
INP
V
INN
Figure 8. ADC Transfer Function
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD73360LAR-REEL | 制造商:Analog Devices 功能描述:AFE General Purpose 6ADC 16-Bit 3.3V 28-Pin SOIC W T/R 制造商:Analog Devices 功能描述:AFE GEN PURPOSE 6ADC 16BIT 3.3V/3.3V/3.3V 28SOIC W - Tape and Reel |
| AD73360LAR-REEL7 | 制造商:Analog Devices 功能描述:AFE General Purpose 6ADC 16-Bit 3.3V 28-Pin SOIC W T/R 制造商:Analog Devices 功能描述:AFE GEN PURPOSE 6ADC 16BIT 3.3V/3.3V/3.3V 28SOIC W - Tape and Reel |
| AD73360LARZ | 功能描述:IC PROCESSOR FRONTEND 6CH 28SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD73360LARZ-REEL | 功能描述:IC PROCESSOR FRONTEND 6CH 28SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD73360LARZ-REEL7 | 功能描述:IC PROCESSOR FRONTEND 6CH 28SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
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