參數(shù)資料
型號(hào): AD73360LAR
廠商: ANALOG DEVICES INC
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Six-Input Channel Analog Front End
中文描述: SPECIALTY TELECOM CIRCUIT, PDSO28
封裝: SOIC-28
文件頁(yè)數(shù): 12/32頁(yè)
文件大?。?/td> 287K
代理商: AD73360LAR
REV. 0
AD73360L
–12–
Table VI. Control Register B Description
7
6
5
4
3
2
1
0
CEE
MCD2
MCD1
MCD0
SCD1
SCD0
DR1
DR0
Bit Name
Description
0
1
2
3
4
5
6
7
DR0
DR1
SCD0
SCD1
MCD0
MCD1
MCD2
CEE
Decimation Rate (Bit 0)
Decimation Rate (Bit 1)
Serial Clock Divider (Bit 0)
Serial Clock Divider (Bit 1)
Master Clock Divider (Bit 0)
Master Clock Divider (Bit 1)
Master Clock Divider (Bit 2)
Control Echo Enable (0 = OFF; 1 = Enabled)
Table VII. Control Register C Description
7
6
5
4
3
2
1
0
RES
RU
PUREF
RES
RES
RES
RES
GPU
Bit Name
Description
0
1
2
3
4
5
6
7
GPU
Reserved
Reserved
Reserved
Reserved
PUREF
RU
Reserved
Global Power-Up Device (0 = Power Down; 1 = Power Up)
Must Be Programmed to Zero (0)
Must Be Programmed to Zero (0)
Must Be Programmed to Zero (0)
Must Be Programmed to Zero (0)
REF Power (0 = Power Down; 1 = Power Up)
REFOUT Use (0 = Disable REFOUT; 1 = Enable REFOUT)
Must Be Programmed to Zero (0)
Table VIII. Control Register D Description
7
6
5
4
3
2
1
0
PUI2
I2GS2
I2GS1
I2GS0
PUI1
I1GS2
I1GS1
I1GS0
Bit Name
Description
0
1
2
3
4
5
6
7
I1GS0
I1GS1
I1GS2
PUI1
I2GS0
I2GS1
I2GS2
PUI2
ADC1:Input Gain Select (Bit 0)
ADC1:Input Gain Select (Bit 1)
ADC1:Input Gain Select (Bit 2)
Power Control (ADC1); 1 = ON, 0 = OFF
ADC2:Input Gain Select (Bit 0)
ADC2:Input Gain Select (Bit 1)
ADC2:Input Gain Select (Bit 2)
Power Control (ADC2); 1 = ON, 0 = OFF
CONTROL REGISTER B
CONTROL REGISTER D
CONTROL REGISTER C
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