參數(shù)資料
型號(hào)： AD73360LAR
廠商： ANALOG DEVICES INC
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Six-Input Channel Analog Front End
中文描述： SPECIALTY TELECOM CIRCUIT, PDSO28
封裝： SOIC-28
文件頁(yè)數(shù)： 6/32頁(yè)
文件大?。?/td> 287K
代理商： AD73360LAR
REV. 0
AD73360L
–6–
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1
2
3
4
5
6
VINP2
VINN2
VINP1
VINN1
REFOUT
REFCAP
Analog Input to the Positive Terminal of Input Channel 2.
Analog Input to the Negative Terminal of Input Channel 2.
Analog Input to the Positive Terminal of Input Channel 1.
Analog Input to the Negative Terminal of Input Channel 1.
Buffered Output of the Internal Reference, which has a nominal value of 1.2 V.
Reference Voltage for ADCs. A Bypass Capacitor to AGND2 of 0.1
μ
F is required for the on-chip
reference. The capacitor should be fixed to this pin. The internal reference can be overdriven by an
external reference connected to this pin if required.
Analog Power Supply Connection.
Analog Ground/Substrate Connection.
Digital Ground/Substrate Connection.
Digital Power Supply Connection.
Active Low-Reset Signal. This input resets the entire chip, resetting the control registers and clearing
the digital circuitry.
Output Serial Clock, whose rate determines the serial transfer rate to/from the AD73360L. It is used
to clock data or control information to and from the serial port (SPORT). The frequency of SCLK is
equal to the frequency of the master clock (MCLK) divided by an integer number
—
this integer num-
ber being the product of the external master clock rate divider and the serial clock rate divider.
Master Clock Input. MCLK is driven from an external clock signal.
Serial Data Output of the AD73360L. Both data and control information may be output on this
pin and are clocked on the positive edge of SCLK. SDO is in three-state when no information is being
transmitted and when SE is low.
Framing Signal Output for SDO Serial Transfers. The frame sync is one bit wide and it is active one
SCLK period before the first bit (MSB) of each output word. SDOFS is referenced to the positive
edge of SCLK. SDOFS is in three-state when SE is low.
Framing Signal Input for SDI Serial Transfers. The frame sync is one-bit wide and it is valid one
SCLK period before the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of
SCLK and is ignored when SE is low.
Serial Data Input of the AD73360L. Both data and control information may be input on this pin and
are clocked on the negative edge of SCLK. SDI is ignored when SE is low.
SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the
output pins of the SPORT are three-stated and the input pins are ignored. SCLK is also disabled inter-
nally in order to decrease power dissipation. When SE is brought high, the control and data registers of
the SPORT are at their original values (before SE was brought low); however, the timing counters and
other internal registers are at their reset values.
Analog Ground Connection.
Analog Power Supply Connection.
Analog Input to the Positive Terminal of Input Channel 6.
Analog Input to the Negative Terminal of Input Channel 6.
Analog Input to the Positive Terminal of Input Channel 5.
Analog Input to the Negative Terminal of Input Channel 5.
Analog Input to the Positive Terminal of Input Channel 4.
Analog Input to the Negative Terminal of Input Channel 4.
Analog Input to the Positive Terminal of Input Channel 3.
Analog Input to the Negative Terminal of Input Channel 3.
7
8
9
10
11
AVDD2
AGND2
DGND
DVDD
RESET
12
SCLK
13
14
MCLK
SDO
15
SDOFS
16
SDIFS
17
SDI
18
SE
19
20
21
22
23
24
25
26
27
28
AGND1
AVDD1
VINP6
VINN6
VINP5
VINN5
VINP4
VINN4
VINP3
VINN3
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