- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375236 > AD73360LAR (ANALOG DEVICES INC) Six-Input Channel Analog Front End PDF資料下載
參數(shù)資料
| 型號： | AD73360LAR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | Six-Input Channel Analog Front End |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 15/32頁 |
| 文件大?。?/td> | 287K |
| 代理商： | AD73360LAR |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
REV. 0
AD73360L
–15–
Control Register F
CRF:0
–
2
CRF:3
CRF:4
–
6
CRF:7
Control Register G
CRG:0
–
5
Input Gain Selection. These bits select the input gain for ADC5. See Table II.
Power Control for ADC5. A 1 in this bit powers up ADC5.
Input Gain Selection. These bits select the input gain for ADC6. See Table II.
Power Control for ADC6. A 1 in this bit powers up ADC6.
Channel Select. These bits are used in association with CRG:6 and CRG:7. If the Reset Analog Modulator bit
(CRG:6) is 1, a 1 in a Channel Select bit location will reset the Analog Modulator for that channel. If the Single-
Ended Enable Mode bit (CRG:7) is 1, a 1 in a Channel Select bit location will put that channel into Single-Ended
Mode. If any channel has its Channel Select bit set to 0, the channel will be set for Differentially-Ended Mode and
will not have its analog modulator reset regardless of the state of CRG:6 and CRG:7.
Reset Analog Modulator. Setting this bit to a 1 will reset the Analog Modulators for any channel whose Channel
Select bit (CRG:0
–
5) is set to 1. This bit should be set to 0 for normal operation.
Single-Ended Enable Mode. Setting this bit to a 1 will enable Single-Ended Mode on any channel whose Channel
Select bit (CRG:0
–
5) is set to 1. Setting this bit to 0 will select Differentially-Ended Input Mode for all channels.
Control Register H
CRH:0
–
5
Invert Select. These bits are used in association with CRH:7. If the Enable Invert Channel Mode bit (CRH:7) is 1,
a 1 in a Channel Select bit location will put that channel into Inverted Mode. If any channel has its Channel Select
bit set to 0, the channel will not be inverted regardless of the state CRH:7.
CRH:6
Test Mode Enable. This bit should be set to 0 to ensure normal operation.
CRH:7
Enable Invert Channel Mode. Setting this bit to a 1 will enable invert any channel whose Channel Select bit
(CRH:0
–
5) is set to 1. Setting this bit to 0 will select Noninverted (Normal) Mode for all channels.
CRG:6
CRG:7
SPORT Register Maps
There are eight control registers for the AD73360L, each eight
bits wide. Table III shows the control register map for the
AD73360L. The first two control registers, CRA and CRB, are
reserved for controlling the SPORT. They hold settings for
parameters such as bit rate, internal master clock rate, and device
count. If two AD73360Ls are cascaded, Registers CRA and
CRB on each device must be programmed with the same setting
to ensure correct operation (this is shown in the programming
examples). The other six registers; CRC through CRH are
used to hold control settings for the Reference, Power Control,
ADC channel, and PGA sections of the device. It is not necessary
that the contents of CRC through CRH on each AD73360L
are similar. Control registers are written to on the negative
edge of SCLK.
Master Clock Divider
The AD73360L features a programmable master clock divider
that allows the user to reduce an externally available master
clock, at pin MCLK, by one of the ratios 1, 2, 3, 4, or 5 to
produce an internal master clock signal (DMCLK) that is used
to calculate the sampling and serial clock rates. The master
clock divider is programmable by setting CRB:4-6. Table XIII
shows the division ratio corresponding to the various bit set-
tings. The default divider ratio is divide-by-one.
Table XIII. DMCLK (Internal) Rate Divider Settings
MCD2
MCD1
MCD0
DMCLK Rate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
MCLK
MCLK/2
MCLK/3
MCLK/4
MCLK/5
MCLK
MCLK
MCLK
Serial Clock Rate Divider
The AD73360L features a programmable serial clock divider
that allows users to match the serial clock (SCLK) rate of the
data to that of the DSP engine or host processor. The maximum
SCLK rate available is DMCLK and the other available rates
are: DMCLK/2, DMCLK/4, and DMCLK/8. The slowest rate
(DMCLK/8) is the default SCLK rate. The serial clock divider
is programmable by setting bits CRB:2
–
3. Table XIV shows the
serial clock rate corresponding to the various bit settings.
Table XIV. SCLK Rate Divider Settings
SCD1
SCD0
SCLK Rate
0
0
1
1
0
1
0
1
DMCLK/8
DMCLK/4
DMCLK/2
DMCLK
相關PDF資料 |
PDF描述 |
|---|---|
| AD73360 | Six-Input Channel Analog Front End(通用6通道模擬輸入前端) |
| AD7339BS | 5 V Integrated High Speed ADC/Quad DAC System |
| AD7339 | 5 V Integrated High Speed ADC/Quad DAC System(高速8位A/D轉換器/四路8位D/A轉換器) |
| AD734 | 10 MHz, 4-Quadrant Multiplier/Divider(10MHz,四象限乘法器/除法器) |
| AD73511 | Low-Power CMOS Analog Front End with Flash based DSP Microcomputer(帶閃速DSP微計算機的單模擬前端) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD73360LAR-REEL | 制造商:Analog Devices 功能描述:AFE General Purpose 6ADC 16-Bit 3.3V 28-Pin SOIC W T/R 制造商:Analog Devices 功能描述:AFE GEN PURPOSE 6ADC 16BIT 3.3V/3.3V/3.3V 28SOIC W - Tape and Reel |
| AD73360LAR-REEL7 | 制造商:Analog Devices 功能描述:AFE General Purpose 6ADC 16-Bit 3.3V 28-Pin SOIC W T/R 制造商:Analog Devices 功能描述:AFE GEN PURPOSE 6ADC 16BIT 3.3V/3.3V/3.3V 28SOIC W - Tape and Reel |
| AD73360LARZ | 功能描述:IC PROCESSOR FRONTEND 6CH 28SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD73360LARZ-REEL | 功能描述:IC PROCESSOR FRONTEND 6CH 28SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD73360LARZ-REEL7 | 功能描述:IC PROCESSOR FRONTEND 6CH 28SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
發(fā)布緊急采購，3分鐘左右您將得到回復。