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參數(shù)資料
| 型號： | AD73360LAR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | Six-Input Channel Analog Front End |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 20/32頁 |
| 文件大?。?/td> | 287K |
| 代理商： | AD73360LAR |
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REV. 0
AD73360L
–20–
In Cascade Mode, both devices must know the number of devices
in the cascade to be able to output data at the correct time.
Control Register A contains a 3-bit field (DC0
–
2) that is pro-
grammed by the DSP during the programming phase. The default
condition is that the field contains 000b, which is equivalent to a
single device in cascade (see Table XVI). However, for cascade
operation this field must contain a binary value that is one less
than the number of devices in the cascade. With a cascade, each
device takes a turn to send an ADC result to the DSP. For
example, the data will be output as Device 2-Channel 1, Device
1-Channel 1, Device 2-Channel 2, Device 1-Channel 2 etc. When
the first device in the cascade has transmitted its channel data
there is an additional SCLK period during which the last device
asserts its SDOFS as it begins its transmission of the next chan-
nel. This will not cause a problem for most DSPs as they count
clock edges after a frame sync and hence the extra bit will be
ignored.
When two devices are connected in cascade there are also restric-
tions concerning which ADC channels can be powered up. In all
cases the cascaded devices must all have the same channels
powered up (i.e., for a cascade requiring Channels 1 and 2 on
Device 1 and Channel 5 on Device 2, Channels 1, 2, and 5
must be powered up on both devices to ensure correct opera-
tion). Figure 18 shows the timing sequence for two devices in
cascade. In all cases Channel 1 of all devices must be powered up.
Table XVI. Device Count Settings
DC2
DC1
DC0
Cascade Length
0
0
0
0
0
1
1
2
Connection of a cascade of devices to a DSP, as shown in Figure
17, is no more complicated than connecting a single device.
Instead of connecting the SDO and SDOFS to the DSP
’
s Rx
port, these are now daisy-chained to the SDI and SDIFS of the
next device in the cascade. The SDO and SDOFS of the second
device in the cascade are connected to the DSP
’
s Rx port to
complete the cascade. SE and
RESET
on both devices are fed
from the signals that were synchronized with the MCLK using
the circuit of Figure 19. The SCLK from only one device need
be connected to the DSP
’
s SCLK input(s) as both devices
will be running at the same SCLK frequency and phase.
1
2
3
4
5
6 7
8 9
10 11 12 13 14 15 16 1
2
3
4
5
6
7 8 9 10 11 12 13 14 15 16 17
DEVICE 2
–
CHANNEL 1
DEVICE 1
–
CHANNEL 1
1
2
3
4 5
6 7
8
DEVICE 2
–
CHANNEL 2
Figure 18. Cascade Timing for a Two-Device Cascade
Cascade Operation
The AD73360L has been designed to support two devices in a
cascade connected to a single serial port (see Figure 17). The
SPORT interface protocol has been designed so that device
addressing is built into the packet of information sent to the
device. This allows the cascade to be formed with no extra hard-
ware overhead for control signals or addressing. A cascade can
be formed in either of the two modes previously discussed.
TFS
DT
DR
RFS
AD73360L
SDIFS
SDI
SCLK
SDO
SDOFS
SCLK
DEVICE 1
MCLK
SE
RESET
AD73360L
74HC74
Q0
Q1
D1
D0
FL0
FL1
ADSP-21xx
DSP
CLK
SDIFS
SDI
SCLK
SDO
SDOFS
DEVICE 2
MCLK
SE
RESET
Figure 17. Connection of Two AD73360Ls Cascaded to
ADSP-21xx
There may be some restrictions in cascade operation due to the
sample clock and the serial clock rate chosen. The formula below
gives an indication of whether the combination of sample rate and
serial clock can be successfully cascaded. This assumes a directly
coupled frame sync arrangement as shown in Figure 12 and does
not take any interrupt latency into account.
1
f
S
6
1
16
17
DeviceCount
SCLK
≥
×
×
+
[((
)
)
]
When using the indirectly coupled frame sync configuration in
cascaded operation it is necessary to be aware of the restrictions
in sending control word data to all devices in the cascade. The
user should ensure that there is sufficient time for all the control
words to be sent between reading the last ADC sample and the
start of the next sample period.
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| AD73360LAR-REEL | 制造商:Analog Devices 功能描述:AFE General Purpose 6ADC 16-Bit 3.3V 28-Pin SOIC W T/R 制造商:Analog Devices 功能描述:AFE GEN PURPOSE 6ADC 16BIT 3.3V/3.3V/3.3V 28SOIC W - Tape and Reel |
| AD73360LAR-REEL7 | 制造商:Analog Devices 功能描述:AFE General Purpose 6ADC 16-Bit 3.3V 28-Pin SOIC W T/R 制造商:Analog Devices 功能描述:AFE GEN PURPOSE 6ADC 16BIT 3.3V/3.3V/3.3V 28SOIC W - Tape and Reel |
| AD73360LARZ | 功能描述:IC PROCESSOR FRONTEND 6CH 28SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD73360LARZ-REEL | 功能描述:IC PROCESSOR FRONTEND 6CH 28SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD73360LARZ-REEL7 | 功能描述:IC PROCESSOR FRONTEND 6CH 28SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
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