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參數(shù)資料
| 型號： | AD1843JS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | CAP 3300PF 100V CERAMIC DISC Y5P |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁數(shù)： | 7/64頁 |
| 文件大?。?/td> | 848K |
| 代理商： | AD1843JS |
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AD1843
REV. 0
–7–
PIN CONFIGURATIONS
80-Lead PQFP
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
80
61
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
AD1843
TOP VIEW
(Not to Scale)
S
S
G
V
D
C
C
V
D
V
D
V
D
V
D
B
G
C
C
B
G
G
B
X
X
GNDD
XCTL1
XCTL0
SYNC3
SYNC2
SYNC1
GNDD
V
DD
RESET
PWRDWN
V
DD
PDMNFT
GNDA
HPOUTL
HPOUTC
HPOUTR
V
CC
SUML
SUMR
V
CC
V
DD
V
CC
SDO
SDFS
GNDD
TSI
TSO
GNDD
V
DD
CS
BM
AUX3R
AUX3L
AUX2R
AUX2L
AUX1R
AUX1L
MICR
MICL
MIN
G
A
F
A
F
L
L
L
L
L
L
L
L
M
L
G
C
V
R
G
L
PIN DESCRIPTION
Serial Interface
Pin Name
PQFP
TQFP
I/O
Description
SCLK
79
99
I/O
Serial Clock. SCLK is a bidirectional signal that supplies the clock as an output
to the serial bus when the Bus Master (BM) pin is driven HI and accepts the clock
as an input when the BM pin is driven LO. When the AD1843 is configured in
master mode, the SCLK frequency may be set to either 12.288 MHz or 16.384 MHz
with the SCF bit in Control Register Address 26.
Serial Data Frame Sync. SDFS is a bidirectional signal that supplies the frame
synchronization signal as an output to the serial bus when the Bus Master (BM)
pin is driven HI and accepts the frame synchronization signal as an input when
the BM pin is driven LO.
Serial Data Input. SDI is used by peripheral devices such as the host CPU or a
DSP to supply control and playback data information to the AD1843. All control
and playback transfers are 16 bits long, MSB first.
Serial Data Output. SDO is used to supply status/control register readback and
capture data information to peripheral devices such as the host CPU or a DSP.
All status/control register readback and capture data transfers are 16 bits long,
MSB first. A three-state output driver is used on this pin.
Bus Master. When BM is tied HI the AD1843 is the serial bus master. The
AD1843 will then supply the serial clock (SCLK) and the frame sync (SDFS)
signals for the serial bus. No more than one device (AD1843/CPU/DSP) should
be configured as the serial bus master. When BM is tied LO, the AD1843 is con-
figured as a bus slave, and will accept the SCLK and SDFS signals as inputs. The
logic level on this pin must not be changed once
RESET
is deasserted (driven HI).
SDFS
2
2
I/O
SDI
80
100
I
SDO
1
1
O
BM
10
12
I
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD1843JST | Serial-Port 16-Bit SoundComm Codec |
| AD1846JP | Low Cost Parallel-Port 16-Bit SoundPort Stereo Codec |
| AD1849KP | Serial-Port 16-Bit SoundPort Stereo Codec |
| AD1851 | 16-Bit, 16×Fs PCM Audio DACs(16位,單片PCM音頻D/A轉(zhuǎn)換器) |
| AD1892JR | Integrated Digital Receiver/Rate Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1843JST | 制造商:AD 制造商全稱:Analog Devices 功能描述:Serial-Port 16-Bit SoundComm Codec |
| AD1845 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Parallel-Port 16-Bit SoundPort Stereo Codec |
| AD1845JP | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 68-Pin PLCC 制造商:Rochester Electronics LLC 功能描述:16 BIT AUDIO CODEC - Bulk 制造商:Analog Devices 功能描述:IC CODEC 16-BIT AUDIO |
| AD1845JP-REEL | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 68-Pin PLCC T/R |
| AD1845JPZ | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 68-Pin PLCC |
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