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參數(shù)資料
| 型號： | AD1843JS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | CAP 3300PF 100V CERAMIC DISC Y5P |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁數(shù)： | 21/64頁 |
| 文件大小： | 848K |
| 代理商： | AD1843JS |
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AD1843
REV. 0
–21–
interval to update the DAC Not Full status bits. Therefore
driver software does not have to make provision for frame-to-
frame delays between control and status information; the infor-
mation in each frame is always up to date.
The AD1843 supports locking to an external clock which may
result in a sample rate that is marginally higher than the nominal
audio standard maximum sample rate of 48 kHz. This is neces-
sary since two crystal-based clock sources are never
perfectly
matched to one another. One is always at a slightly higher fre-
quency. The AD1843 conversion channels have been designed
to support sample rates that are up to 2.1% higher than 48 kHz
(i.e., 49 kHz), referenced to the AD1843’s clock input on
XTALI, when all conversion channels are simultaneously run-
ning. Even higher rates can be supported when all channels are
not running simultaneously. See the “Conversion Rates” sec-
tion above for additional details. The serial interface must also
allow for this higher sample rate with a frame sync (SDFS) rate
that is at least as high as the sample rate in 16 slot per frame
mode, or half as high as the sample rate in 32 slot per frame
mode. When the AD1843 is bus master, the SCLK frequency
is either 12.288 MHz or 16.384 MHz, which allows for up to
48 kHz or 64 kHz sampling rates, respectively.
The AD1843 Control Registers are read and written by trans-
mitting a read/write request bit along with the Control Register
address in the slot 0 Control Word. When a read is requested,
the contents of the Control Register addressed is transmitted
out during slot 1 of the following frame. When a write is re-
quested, data to be written must be transmitted to the AD1843
in slot 1, and the former contents of the control register are
transmitted out during slot 1 of the following frame. Unless oth-
erwise noted, Control Register writes do not take effect until the
current round of six communication TDM time slots concludes.
Equivalently, unless otherwise noted, Control Register writes do
The following sections describe the bit assignments for all time
slots.
IGNORED
3-STATED
CONTROL WORD
STATUS WORD
REGISTER DATA
REGISTER DATA
DAC1 LEFT
ADC LEFT
DAC1 RIGHT
ADC RIGHT
DAC2 LEFT
0s
DAC2 RIGHT
0s
IGNORED
3-STATED
SDI
SDO
16-BIT
STEREO
DON'T
CARE
IGNORED
3-STATED
CONTROL WORD
STATUS WORD
REGISTER DATA
REGISTER DATA
IGNORED
3-STATED
0s
DAC1R
DON'T
CARE
DAC2L
DAC2R
DON'T
CARE
0s
DAC1L
DON'T
CARE
0s
0s
ADCL
ADCR
SDI
SDO
8-BIT
STEREO
IGNORED
3-STATED
CONTROL WORD
STATUS WORD
REGISTER DATA
REGISTER DATA
DAC1
ADC LEFT
DON'T CARE
ADC RIGHT
DAC2
0s
DON'T CARE
0s
IGNORED
3-STATED
SDI
SDO
16-BIT
MONO
DAC1, DAC2
IGNORED
3-STATED
CONTROL WORD
STATUS WORD
REGISTER DATA
REGISTER DATA
DON'T CARE
DON'T CARE
0s
DAC2
0s
DON'T
CARE
0s
DON'T
CARE
0s
DAC1
ADCL
ADCR
IGNORED
3-STATED
SDI
SDO
8-BIT
MONO
DAC1, DAC2
THE DIAGRAM ABOVE IS INTENDED TO BE ILLUSTRATIVE OF THE MORE COMMONLY USED CONFIGURATIONS. ADC LEFT, ADC RIGHT, DAC1
AND DAC2 CAN BE INDIVIDUALLY ASSIGNED TO 8-BIT OR 16-BIT SAMPLE WIDTH, AND DAC1 AND DAC2 CAN BE INDIVIDUALLY ASSIGNED
TO STEREO OR MONO MODE. EACH AD1843 CONSUMES 6 TMD SLOTS (REQUIRING 96 SCLK PERIODS), LEAVING 10 TDM SLOTS
UNUSED IN A 16 SLOT FRAME.
NOTE THAT BECAUSE THE SERIAL INTERFACE AND THE ADC AND DACS ARE IN GENERAL ASYNCHRONOUS, NOT EVERY CAPTURE OR
PLAYBACK TIME SLOT WILL CONTAIN VALID DATA. THE HOST PROCESSOR MUST POLL THE STATUS WORD TO DETERMINE WHETHER
THE ADC DATA IS VALID AND WHETHER THE DAC IS REQUESTING ADDITIONAL SAMPLES.
TIME
SLOT 0
TIME
SLOT 1
TIME
SLOT 2
TIME
SLOT 3
TIME
SLOT 4
TIME
SLOT 5
SCLK
SDFS
16 BITS
Figure 11. AD1843 Slot Assignments
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD1843JST | Serial-Port 16-Bit SoundComm Codec |
| AD1846JP | Low Cost Parallel-Port 16-Bit SoundPort Stereo Codec |
| AD1849KP | Serial-Port 16-Bit SoundPort Stereo Codec |
| AD1851 | 16-Bit, 16×Fs PCM Audio DACs(16位,單片PCM音頻D/A轉(zhuǎn)換器) |
| AD1892JR | Integrated Digital Receiver/Rate Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1843JST | 制造商:AD 制造商全稱:Analog Devices 功能描述:Serial-Port 16-Bit SoundComm Codec |
| AD1845 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Parallel-Port 16-Bit SoundPort Stereo Codec |
| AD1845JP | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 68-Pin PLCC 制造商:Rochester Electronics LLC 功能描述:16 BIT AUDIO CODEC - Bulk 制造商:Analog Devices 功能描述:IC CODEC 16-BIT AUDIO |
| AD1845JP-REEL | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 68-Pin PLCC T/R |
| AD1845JPZ | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 68-Pin PLCC |
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