參數(shù)資料
型號(hào)： AD1843JS
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： CAP 3300PF 100V CERAMIC DISC Y5P
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝： PLASTIC, QFP-80
文件頁(yè)數(shù)： 43/64頁(yè)
文件大?。?/td> 848K
代理商： AD1843JS
AD1843
REV. 0
–43–
1 = Clocks are referenced to the input on pin SYNC3 (Sync 3 Clock Input).
Sample clock frequency is defined by C3VID and C3M7:0.
Sample clock phase is locked to SYNC3 and cannot be shifted.
Bit clock frequency is defined by bits C3M7:0 and C3P200 unless in Video Lock Mode
(C3VID set to “1”) where the Bit clocks are not produced.
Control Register Addresses 23, 24 and the C3X8/7 bits are ignored.
Clock Generator 3 Video Lock Mode. This bit is used to select between lock modes when the Clock Generator 3 is
referenced to SYNC3 (C3REF set to “1”). This bit should be reset to “0” if C3REF is reset to “0.” When reset to
“0,” Clock Generator 3 is in
normal
lock mode where the Conversion clock will be frequency and phase locked to
SYNC3, and the Bit clock frequency is chosen using bits C3M7:0 and C3P200. When set to “1,” Clock Generator 3
is in
video
lock mode, where the Conversion clock frequency is selected using bits C3M7:0, and a Bit clock is not produced.
Clock Generator 3 PLL Loop Gain Select. If reset to “0,” this bit selects finite PLL loop gain, and if set to “1,” this
bit selects infinite PLL loop gain. This bit should nominally be reset to “0.” Setting it to “1” may enhance the PLL’s
ability to lock to certain SYNC3 inputs, but it may also increase conversion noise.
Clock Generator 3 Bit Clock +200 Frequency Modifier. When set to “1,” the Bit clock driven out of pin BIT3 will
have a frequency that is 200 Hertz greater than the frequency selected through bit C3M7:0. This bit is ignored when
in Video Lock Mode (C3VID set to “1”). C3P200 only modifies the bit clock driven on the BIT3 pin.
Clock Generator 3 Conversion Clock 8/7 Frequency Modifier. When set to “1,” the Conversion clock frequency gen-
erated will be 8/7 times the value programmed in Control Register Address 23. This bit is ignored when clocks are
referenced to SYNC3 (C3REF set to “1”).
Clock Generator 3 Conversion Clock Pin (CONV3) Frequency Select. When set to “1,” the frequency driven on to
the CONV3 pin will be 128 times the conversion rate. When reset to “0,” the frequency driven on to the CONV3 pin
will be the same as the conversion rate. C3C128 only modifies the clock frequency driven on the CONV3 pin.
Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.
Clock Generator 3 Clock Rate Modifiers.
When not in Video Lock Mode (C3REF and C3VID are not both set to “1”):
Bits C3M7:0 select the Bit clock rate which will be driven out on pin BIT3. Using the following table, the least sig-
nificant four bits (C3M3:0) are programmed to the desired Bit clock rate, and the most significant four bits
(C3M7:4) must be programmed to the Conversion clock rate established using Control Register Address 23 and the
C3X8/7 bit. If the actual Conversion clock differs from the value selected by C3M7:4, then the resultant Bit clock
will be different from the rate selected by the ratio of the C3M7:4 selected rate to the Control Register Address 23
plus the C3X8/7 bit actual rate.
C3M3:0
Bit Clock Frequency*
0000
2,400
Hertz
0001
4,800
0010
7,200
0011
9,600
0100
12,000
0101
14,400
0110
16,800
0111
19,200
1000
21,600
1001
24,000
1010
26,400
1011
28,800
1100
Reserved
1101
Reserved
1110
Reserved
1111
See Below
C3VID
C3PLLG
C3P200
C3X8/7
C3C128
res
C3M7:0
C3M7:4
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Conversion (Sample) Rate
7,200
8,400
9,000
9,600
11,200
12,000
12,800
7,200
×
8/7
9,000
×
8/7
9,600
×
8/7
12,000
×
8/7
Reserved
Reserved
Reserved
Reserved
See Below
Hertz
*Bit clock frequencies listed will be increased by 200 Hz if C3P200 is set to “1.”
When C3M7:4 is programmed to “1111” and C3M3:0 is programmed to “1111,” the Bit clock rate will be 128 times
the Conversion rate.
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