參數(shù)資料
型號(hào)： AD1843JS
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： CAP 3300PF 100V CERAMIC DISC Y5P
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝： PLASTIC, QFP-80
文件頁(yè)數(shù)： 47/64頁(yè)
文件大?。?/td> 848K
代理商： AD1843JS
AD1843
REV. 0
–47–
DA2SM
DAC2 Stereo/Mono Mode Select. When in stereo mode, data transmitted to the AD1843 during slot 4 is
used by DAC2 left and data transmitted to the AD1843 during slot 5 is used by DAC2 right. When in
mono mode, data transmitted to the AD1843 during slot 4 is used by both DAC2 left and right, and data
transmitted to the AD1843 during slot 5 is ignored. (Note: slot 0 is assumed to be the first slot.)
0
= Stereo Mode
1 = Mono Mode
DAC1 Stereo/Mono Mode Select. When in stereo mode, data transmitted to the AD1843 during slot 2 is
used by DAC1 left and data transmitted to the AD1843 during slot 3 is used by DAC1 right. When in
mono mode, data transmitted to the AD1843 during slot 2 is used by both DAC1 left and right, and data
transmitted to the AD1843 during slot 3 is ignored. (Note: slot 0 is assumed to be the first slot.)
0
= Stereo Mode
1 = Mono Mode
DAC2 (Left and Right Channels) Data Format Select.
00
= 8-bit Unsigned Linear PCM
01 = 16-bit Signed Linear PCM
10 = 8-bit
μ
-Law Companded
11 = 8-bit A-Law Companded
DAC1 (Left and Right Channels) Data Format Select.
00
= 8-bit Unsigned Linear PCM
01 = 16-bit Signed Linear PCM
10 = 8-bit
μ
-Law Companded
11 = 8-bit A-Law Companded
SCLK Frequency Select. Changes to this bit do not take effect until shortly after the sixth slot (the final slot
owned) is completed. Relevant when the AD1843 is in Master Mode only.
0
= 12.288 MHz
1 = 16.384 MHz
Frame Size Select. Selects the number of slots per frame. Changes to this bit do not take effect until the
time specified by the FRST bit.
0
= 32 Slots per Frame
1 = 16 Slots per Frame
Frame Size Change Timing. Selects the point in time when FRS takes effect.
0
= Frame Size Changes Once the Current Frame is Complete
1 = Frame Size Changes Immediately, Beginning with the Current Frame
ADC Transmit Lock Mode Select. When this bit is set to “1,” ADC transmit lock mode is entered. In this
mode, left and right ADC samples are transmitted during a frame only if both left and right samples are
ready to be transmitted. When not in ADC transmit lock mode, left and right samples are transmitted as
they individually become available. Note that even if left and right ADCs are programmed to the same
sample rate, unless the AD1843 is in transmit lock mode, ADC samples will not necessarily be transmitted
paired together in a TDM frame. This bit should be set to “1” only if both ADCs are powered down and
only if both ADCs will be programmed to the sample rate once they are enabled. This bit may be reset to
“0” at any time. While in ADC transmit lock mode, both ADCs must be enabled and disabled simulta-
neously (write to Control Register Address 27 must set ADLEN and ADREN both to “0” or to “1”).
0
= ADC Transmit Lock Mode Disabled
1 = ADC Transmit Lock Mode Enabled
ADC Right Channel Data Format Select.
00
= 8-bit Unsigned Linear PCM
01 = 16-bit Signed Linear PCM
10 = 8-bit
μ
-Law Companded
11 = 8-bit A-Law Companded
ADC Left Channel Data Format Select.
00
= 8-bit Unsigned Linear PCM
01 = 16-bit Signed Linear PCM
10 = 8-bit
μ
-Law Companded
11 = 8-bit A-Law Companded
Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.
Initial default state after reset: 0000 0000 0000 0000 (0000 hex). Cleared to default and cannot be written
to when: the
RESET
pin is asserted LO; or when the
PWRDWN
pin is asserted LO.
DA1SM
DA2F1:0
DA1F1:0
SCF
FRS
FRST
ADTLK
ADRF1:0
ADLF1:0
res
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