- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375230 > AD1843JS (ANALOG DEVICES INC) CAP 3300PF 100V CERAMIC DISC Y5P PDF資料下載
參數(shù)資料
| 型號(hào)： | AD1843JS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | CAP 3300PF 100V CERAMIC DISC Y5P |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁數(shù)： | 55/64頁 |
| 文件大?。?/td> | 848K |
| 代理商： | AD1843JS |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁當(dāng)前第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
AD1843
REV. 0
–55–
in which the valid flag is first asserted, and continues to be
asserted in future frames, depends on how the AD1843 is
configured, i.e., the sample rates selected, the frame size
selected, and how the shared digital resources within the
AD1843 are internally allocated to process all conversion
channels. Note that because of this, two ADCs which are
enabled during the same frame and share the same sample
rate clock, will not necessarily transmit data during the same
frames thereafter, even though their analog inputs will always
be sampled at the same instant in time. The two ADCs will
transmit data during the same frame if ADTLK (Control
Register Address 26, Bit 4) is set HI. See the description of
the ADTLK bit for restrictions.
If mixing is enabled, either a mix from DAC2 to DAC1 or a
mix from an ADC input to a DAC output, then the mix will
begin during the same TDM frame that it is enabled.
8.
Configure conversion resources while they are enabled
.
Once enabled, DAC output gain/attenuation levels may be
changed using Control Register Addresses 3 through 10.
These registers are forced to their default of full attenuation
whenever the resource they control is either in standby or
completely powered down. Note that while a conversion re-
source is enabled, all configuration selections related to it
may be changed except those outlined in Step 6.
The AD1843 Start-Up Sequence state diagram is shown in
Figure 17.
APPLICATIONS CIRCUITS
The AD1843 SoundComm Codec has been designed to require
a minimum of external circuitry. The recommended circuits are
shown in Figures 18 through 34. Analog Devices estimates that
the total cost of all the components shown in these Figures (in-
cluding the crystal but not including the DAA) to be less than
$6 in 10,000 piece quantities.
Industry-standard compact disc “l(fā)ine-levels” are 2 V
rms cen-
tered around analog ground. (For other audio equipment, “l(fā)ine
level” is much more loosely defined.) The AD1843 SoundComm
Codec is a +5 V analog supply powered device. Nominal line
level voltage swings for the AD1843 are defined to be 1 V rms
(ADRFLT and ADLFLT = 0) for a sine wave ADC input and
0.707 V rms for a sine wave DAC output (DA2FLT = 0). Thus,
2 V rms input analog signals must be attenuated and either cen-
tered around the reference voltage intermediate between 0 V
and +5 V or ac-coupled. The CMOUT pin will be at this inter-
mediate voltage, nominally 2.25 V. It has limited drive but can
be used as a voltage datum to an op amp input. CMOUT load-
ing should be minimized to limit any audible clicks and pops.
Note that dc-coupled inputs are not recommended, as they pro-
vide no performance benefits with the AD1843 architecture.
Furthermore, dc offsets on inputs create the potential for clicks
when changing the input mix gain/attenuation/mute.
The
RESET
pin must be asserted at or shortly after power up in
order to initialize the AD1843 Control Registers to their default
states. If the AD1843 will not be used immediately, and if it is
desired to utilize the mono input to mono output feedthrough
feature, it is essential that the mono output is ac-coupled to pre-
vent audible pops and clicks. It is recommended that all outputs
are ac coupled, as standing current in output loads or in the
voltage reference will contribute to audible pops and clicks.
A circuit for 2 V rms line-level inputs is shown in Figure 18.
Note that this is a divide-by-two resistive divider, and that the
line input is being used in a single-ended configuration. The
1
μ
F ac-coupling capacitor may be of any type (tantalum is a
popular choice).
LINLP
5.1k
1μF
5.1k
LINRP
5.1k
1μF
5.1k
1nF
1nF
Figure 18. AD1843 2 V rms Single-Ended Line-Level
Input Circuit
If line-level inputs are already at the 1 V rms levels expected by
the AD1843, the circuit shown in Figure 19 below should be
used. Note that when single-ended line inputs are desired, only
the LINRP and LINLP pins are used. DO NOT use the
LINRN or LINLN pins if the line input is single-ended.
LINLP
1μF
1μF
LINRP
Figure 19. AD1843 1 V rms Single-Ended Line-Level
Input Circuit
The three auxiliary inputs, the SUM inputs, and the mono in-
put of the AD1843 present an input impedance which is lower
than the stereo line input. The circuit shown in Figure 20
should be used with 2 V rms swings on these inputs. With 1 V
rms swings, the circuit in Figure 19 above should be used.
4.1k
1μF
3.3k
AUX1L
AUX2L
AUX3L
SUML
1nF
4.1k
1μF
3.3k
1nF
MIN
4.1k
1μF
3.3k
AUX1R
AUX2R
AUX3R
SUMR
1nF
Figure 20. AD1843 2 V rms Aux, SUM, and Mono Input
Circuits
For optimal performance, the AD1843 includes provision for a
differential configuration of the LIN inputs. Figure 21 illus-
trates a simple single-ended to differential converter. For the
best noise immunity, the circuitry to the left of the dotted line
should be located as close to the driving signal source as possible.
The 0.9K resistor and the 1000 pF capacitor are manda-
tory when using the LINRN and/or the LINLN inputs.
Furthermore, the 0.9K resistor and the 1000 pF NPO capacitor
should be located as close to the AD1843 as possible. If the
output range of the source does not match that of the AD1843
input, the op amp gain setting resistor values should be scaled
to match the source voltage range to the AD1843 input voltage
range.
Inexpensive feedback capacitors can be added (as shown in the
Figure 21 with dotted lines) for additional noise filtering (6 dB
per octave). Without the additional filter capacitor, there is a
single antialiasing pole at approximately 160 kHz. There is
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD1843JST | Serial-Port 16-Bit SoundComm Codec |
| AD1846JP | Low Cost Parallel-Port 16-Bit SoundPort Stereo Codec |
| AD1849KP | Serial-Port 16-Bit SoundPort Stereo Codec |
| AD1851 | 16-Bit, 16×Fs PCM Audio DACs(16位,單片PCM音頻D/A轉(zhuǎn)換器) |
| AD1892JR | Integrated Digital Receiver/Rate Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1843JST | 制造商:AD 制造商全稱:Analog Devices 功能描述:Serial-Port 16-Bit SoundComm Codec |
| AD1845 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Parallel-Port 16-Bit SoundPort Stereo Codec |
| AD1845JP | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 68-Pin PLCC 制造商:Rochester Electronics LLC 功能描述:16 BIT AUDIO CODEC - Bulk 制造商:Analog Devices 功能描述:IC CODEC 16-BIT AUDIO |
| AD1845JP-REEL | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 68-Pin PLCC T/R |
| AD1845JPZ | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 68-Pin PLCC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。