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參數(shù)資料
| 型號(hào)： | AD1843JS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | CAP 3300PF 100V CERAMIC DISC Y5P |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁數(shù)： | 48/64頁 |
| 文件大?。?/td> | 848K |
| 代理商： | AD1843JS |
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REV. 0
–48–
AD1843
Address 27
Codec Configuration—Channel Power Down
Data 15
Data 14
Data 13
Data 12
Data 11
Data 10
Data 9
Data 8
DFREE
res
res
DDMEN
res
res
DA2EN
DA1EN
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
ANAEN
HPEN
res
AAMEN
res
res
ADREN
ADLEN
DFREE
Digital Resource Free. When set to “1,” this bit reduces the level of power down normally achieved by asserting the
power down bits in this Control Register. However, it allows the digital resources of channels powered down to be
partially transferred to the remaining enabled channels and thus permits conversion rates higher than the 48 kHz
nominal maximum. See the “Supported Conversion Rates” section.
0
= Power Down of Digital Resources is Complete
1 = Power Down of Digital Resources is Incomplete, Freeing Transferable Resources to Enabled Channels
DAC2 to DAC1 Mix Enable/Power Down. When reset to “0,” Control Register Address 3 is cleared to its default
and cannot be written.
0
= Mix is Powered Down
1 = Mix is Enabled
DAC2 (Left and Right Channels) Enable/Power Down. When this bit is reset to “0,” DAC2 is powered down and
serial interface requests for samples (see slot 0) will cease immediately. When this bit is set to “1,” DAC2 is enabled
and requests for samples resume on the next frame. Conversions will not actually begin until the first rising edge of
the conversion clock (CONV pin) after the sixth rising edge of frame sync (SDFS pin) after this bit is set to “1.” This
delay allows the four word stereo input buffer for DAC2 to be filled before conversions begin and allows the serial in-
terface to synchronize with the conversion clock, which is potentially already running. This delay also allows DACs
on multiple AD1843s sharing the same frame sync to begin conversions synchronously, providing they are enabled at
any time during the same frame. When this bit is reset to “0,” Control Register Address 10, which is the Output
Level Control Register for DAC2, is cleared to default and cannot be written.
0
= DAC2 is Powered Down, Control Register Address 10 (DAC2 Output Level Control) is Cleared
1 = DAC2 is Enabled
DAC1 (Left and Right Channels) Enable/Power Down. When this bit is reset to “0,” DAC1 is powered down and
serial interface requests for samples (see slot 0) will cease immediately. When this bit is set to “1,” DAC1 is enabled
and requests for samples resume on the next frame. Conversions will not actually begin until the first rising edge of
the conversion clock (CONV pin) after the sixth rising edge of frame sync (SDFS pin) after this bit is set to “1.” This
delay allows the four word stereo input buffer for DAC1 to be filled before conversions begin and allows the serial in-
terface to synchronize with the conversion clock, which is potentially already running. This delay also allows DACs
on multiple AD1843s sharing the same frame sync to begin conversions synchronously, providing they are enabled at
any time during the same frame. When this bit is reset to “0,” Control Register Address 9, which is the Output Level
Control Register for DAC1, is cleared to default and cannot be written.
0
= DAC1 is Powered Down, Control Register Address 9 (DAC1 Output Level Control) is Cleared
1 = DAC1 is Enabled
Analog Channel Enable/Power Down. If this bit is reset to “0,” all analog conversion circuitry (related to bits
DA1EN, DA2EN, ADLEN, ADREN, DDMEN and AAMEN) will be powered down. When reset to “0,” the only
conversion channels usable (but must be enabled separately) are the digital resampling paths. Since resetting this bit
to “0” powers down the analog ADC, DAC1, DAC2 and analog mixers, their related output level Control Register
Addresses 4 through 7, half of 8, 9 and 10 are cleared and cannot be written while ANAEN remains “0.”
0 = Analog Channels are Powered Down, Control Register Addresses 4 through 7, half of 8, 9 and 10 are Cleared to
Default (Digital to Digital Still Possible)
1
= Analog DAC and ADC Paths are Controlled by DA1EN, DA2EN, ADLEN, ADREN, DDMEN and AAMEN
Headphone Enable/Power Down.
0 = Headphone Output is Powered Down
1
= Headphone Output is Enabled
Analog Input to Analog Output Mix Enable/Power Down. When reset to “0,” Control Register Addresses 4 - 7 and
half of Control Register Address 8 are cleared and cannot be written.
0
= Mix is Powered Down
1 = Mix is Enabled
DDMEN
DA2EN
DA1EN
ANAEN
HPEN
AAMEN
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD1843JST | 制造商:AD 制造商全稱:Analog Devices 功能描述:Serial-Port 16-Bit SoundComm Codec |
| AD1845 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Parallel-Port 16-Bit SoundPort Stereo Codec |
| AD1845JP | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 68-Pin PLCC 制造商:Rochester Electronics LLC 功能描述:16 BIT AUDIO CODEC - Bulk 制造商:Analog Devices 功能描述:IC CODEC 16-BIT AUDIO |
| AD1845JP-REEL | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 68-Pin PLCC T/R |
| AD1845JPZ | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 68-Pin PLCC |
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