參數(shù)資料
型號(hào): 84221
英文描述: 84221 Quad 10/100 Mbps TX/FX/10BT (PHY) manual 1/99
中文描述: 84221四10/100 Mbps的TX/FX/10BT(PHY)的手冊(cè)1 / 99
文件頁(yè)數(shù): 8/70頁(yè)
文件大?。?/td> 1017K
代理商: 84221
8
MD400184/A
84221
1.0 PIN DESCRIPTION (cont’d)
Miscellaneous
Pin #
Pin Name
I/O
Description
95
ANEG
I
AutoNegotiation Enable Input.
0.12, enables AutoNegotiation for all channels.
This digital input, ANDed with register bit
1 = AutoNegotiation On & Combined with Speed and Duplex pins,
control advertisement. Please refer to Table 1 for the
different combinations.
0 = Off
1
128
122
121
SPEED_[3:0]
I
Speed Selection Input.
select speed in each corresponding channel. Please refer to Table 1 for the
different combinations.
These digital inputs, ANDed with register bit 0.13,
1 = 100 Mbps Mode
0 = 10 Mbps Mode
114
115
116
117
DPLX_[3:0]
I
Duplex Selection Input.
select the duplex mode in EACH corresponding channel. They control
advertisement when ANEG is enabled. Please refer to Table 1 for the
different combinations.
These digital inputs, ORed with register bit 0.8,
1 = Full Duplex Mode
0 = Half Duplex Mode
89
REPEATER
I
Repeater Mode Enable Input.
17.14, enables repeater mode for ALL channels.
This digital input, ORed with register bit
1 = Repeater Mode Enabled
0 = Normal Operation
54
AD_REV
I
Pullup
Address Reverse Input.
1 = Normal
In this mode, physical ports 0-3 are mapped to MI
addresses 0-3 in the same order.
0 = Reverse Address Mode Select
In this mode, physical ports 0-3 are mapped to MI addresses 3-0
respectively. This is the reverse to the normal order.
120
RESET
I
Pullup
Hardware Reset Input.
1 = Normal
0 = Device In Reset State
(Reset is complete 50 ms after RESET goes high).
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