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參數(shù)資料
| 型號(hào)： | 84221 |
| 英文描述： | 84221 Quad 10/100 Mbps TX/FX/10BT (PHY) manual 1/99 |
| 中文描述： | 84221四10/100 Mbps的TX/FX/10BT（PHY）的手冊(cè)1 / 99 |
| 文件頁(yè)數(shù)： | 48/70頁(yè) |
| 文件大?。?/td> | 1017K |
| 代理商： | 84221 |
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48
MD400184/A
84221
these pins to VDD or VSS as shown in Table 23. Note
that these pins SHOULD NOT FLOAT but must be
connected either High or Low for proper operation.
In order to obtain the “Default Mode of Operation”, ie:
Auto-negotiation enabled, 100MBs, and Half Duplex; the
ANEG, SPEED_[3:0], and DPLX_[3:0] pins should be set
to 1,1,0 respectively.
Table 23. Hardware Configuration
4.9 LONG CABLE
IEEE 802.3 specifies that 10BaseT and 100BaseTX
operate over twisted pair cable lengths from 0 to 100
meters. The squelch levels can be reduced by 4.5 dB if
the receive level adjust bit is appropriately set in the MI
serial port Channel Configuration register, which will allow
the 84221 to operate with up to 150 meters of twisted pair
cable. The equalizer is already designed to accomodate
between 0 to 150 meters of cable.
4.10 CLOCK
The 84221 requires a 25 MHz reference frequency for
internal signal generation in MII mode, and 50 MHz in
RMII mode. The appropriate reference frequency must
be applied to the CLKIN pin.
4.11 LED DRIVERS
The LED[3:0] outputs can all drive LED’s tied to VDD as
shown in Figure 12 and Figure 13. In addition, the
LED[3:0] outputs can drive LED’s tied to GND as well.
The LED definitions assume that the LED outputs are tied
to VDD, active low signals (otherwise the LED outputs will
indicate their respective opposite events.)
The LEDDEF pin determines the default settings for
LED[3:0]. If LEDDEF = 0, the default functions for
LED[3:0] are Link 100, Activity, Full Duplex, and Link 10,
respectively. If LEDDEF = 1, the LED functions for
LED[3:0] are forced to LINK + ACTIVITY Collision, Full
Duplex and 10/100 Mbps operation, respectively. Table 5
defines the LED functions. Table 4 defines the LED
events.
The LED[3:0] outputs can also drive other digital inputs.
Thus, LED[3:0] can also be used as digital outputs whose
function can be user defined and controlled through the
MI serial port.5V Compatible I/O Operation.
4.12 5V COMPATIBLE I/O OPERATION
The input and output pins of the 84221 are tolerant of
signal levels up to a maximum of 5.5V (including
overshoot etc.). This allows the transceiver to be
operated with 5V controllers that have TTL I/O
characteristics (0.8 to 2.0V Input levels) without the use of
levelshifters or other interfaces.
Controllers and other system components may be
operate with 5V supplies and all inter-chip signals may be
connected directly to the 84221. All required external
logic levels must retain TTL compatability since the 84221
outputs are not guaranteed to achieve higher than 2.3V
with a load of 10ma. However, the inputs of the 84221 will
tolearte TTL or CMOS logic levels being driven into the
device.
This should make replacement of the Physical Layer
transceivers in existing designs quite simple since any 5V
devices do not need to be changed.
4.13 POWER SUPPLY DECOUPLING
All VDD's on each individual side should be connected
together (grouped) and tied to a power plane, as close as
possible to the 84221 supply pins. If the VDD's vary in
potential by even a small amount, noise and latchup can
result. The 84221 VDD pins should be kept to within 50
mV of each other.
All GND's should be connected as close as possible to
the device with a large ground plane. If the GND's vary in
potential by even a small amount, noise and latchup can
result. The GND pins should be kept to within 50 mV of
each other.
Configuration
State
Auto-
Negotiate
Speed
Duplex
Normal
(POC/RESET)
Config Pins
Enabled
Advertise
10/100
SPEED_
[3:0]=1
10MBs
Advertise
Full/Half
DPLX_
[3:0]=0
Full
ANEG=1
Complement
State
Config Pins
Disabled
ANEG=0
SPEED_
[3:0]=0
DPLX_
[3:0]=1
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