參數(shù)資料
型號: 84221
英文描述: 84221 Quad 10/100 Mbps TX/FX/10BT (PHY) manual 1/99
中文描述: 84221四10/100 Mbps的TX/FX/10BT(PHY)的手冊1 / 99
文件頁數(shù): 47/70頁
文件大?。?/td> 1017K
代理商: 84221
MD400184/A
47
84221
4.4 TRANSMITTER DROOP
The IEEE 802.3 specification has a transmitter output
droop requirement for 100BaseTX. Since the 84221 TP
output is a current source, it has no perceptible droop by
itself. However, the open circuit inductance of the
transformer added to the device transmitter output as
shown in Figure 12 will cause droop to appear at the
transmit interface to the TP wire. If the transformer
connected to the 84221 outputs meets the requirements
in Table 20, the transmit interface to the TP cable will meet
the IEEE 802.3 droop requirements.
4.5 CONTROLLER INTERFACE
4.5.1 General
The 84221 interfaces seemlessly to any standard
controller that has a RMII interface that fully complies with
the specification created by the RMII consortium.
4.5.2 Clocks
The 84221 requires a 50 MHz clock that must be applied
to the CLKIN input. Data is clocked in on the rising edge
of CLKIN.
4.5.3 RMII Disable
The RMII outputs can be placed in the high impedance
state and inputs disabled by setting the RMII disable bit in
the MI serial port Control register. When this bit is set to
the disable state, the TP outputs are both disabled and
transmission is inhibited. The default value of this bit
when the device powers up or is reset is dependent on
the device address. If the device address latched into
PHYAD[4:0] at reset is 11111, it is assumed that the
device is being used in applications where there maybe
more than one device sharing the RMII bus, like external
PHY’s or adapter cards, so the device powers up with the
RMII interface disabled. If the device address latched into
PHYAD[4:0] at reset is not 11111, it is assumed that the
device is being used in an application where it is the only
device on the RMII bus, like hubs, so the device powers
up with the RMII interface enabled.
4.6 REPEATER APPLICATIONS
4.6.1 RMII Based Repeaters
The 84221’s RMII interface can interface to any repeater
controller with a RMII interface. The 84221 does add
additional latency since the internal data path goes
through the unexposed MII interface. So any repeater
implementation has to carefully consider the repeater bit
budget impact due to the additional latency.
4.7 SERIAL PORT
4.7.1 General
The 84221 has a MI serial port to set all of the devices's
configuration inputs and read out the status outputs. Any
external device that has an IEEE 802.3 compliant MI
interface can connect directly to the 84221 without any
glue logic, as shown in Figure 12 and Figure 13.
As described earlier, the MI serial port consists of five
lines: MDC, MDIO, and PHYAD[4:2]. However, only 2
lines, MDC and MDIO, are needed to shift data in and out.
PHYAD[4:2] define the three most significant bits of the
PHY address, as described in the Section 4.7.2, Serial
Port Addressing Section.
4.7.2 Serial Port Addressing
The device address for the MI serial port is selected by
connecting the PHYAD[4:2] pins to the desired value. The
PHYAD[1:0] addresses are internally hardwired for each
channel as shown in both Tables 5 and 7.
4.8 UNMANAGED PORT CONFIGURATION
The 84221 has configuration inputs which can “over-ride”
the default configuration state obtained on POWER-UP or
RESET of the device. Use of these pins ANEG,
SPEED_[3:0], and DPLX_[3:0] allow selection of Global
Autonegotiation, Individual Port Speed (10/100), and
Individual Port Duplex (Full/Half), by properly strapping
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