參數(shù)資料
型號(hào): 84221
英文描述: 84221 Quad 10/100 Mbps TX/FX/10BT (PHY) manual 1/99
中文描述: 84221四10/100 Mbps的TX/FX/10BT(PHY)的手冊(cè)1 / 99
文件頁數(shù): 23/70頁
文件大?。?/td> 1017K
代理商: 84221
MD400184/A
23
84221
2.15 RECEIVE POLARITY CORRECTION
2.15.1 100 Mbps
No polarity detection or correction is needed in 100 Mbps
mode.
2.15.2 10 Mbps
The polarity of the signal on the TP receive input is
continuously monitored. If one SOI pulse indicates
incorrect polarity on the TP receive input, the polarity is
internally determined to be incorrect, and the reverse
polarity bit is set in the MI serial port Channel Status
Output register.
The 84221 will automatically correct for the reverse
polarity condition provided that the autopolarity feature is
not disabled.
2.16 FULL DUPLEX MODE
2.16.1 100 Mbps
Full Duplex mode allows transmission and reception to
occur simultaneously.
The device can be either forced into Half or Full Duplex
mode, or the device can detect either Half or Full Duplex
capability from a remote device and automatically place
itself in the correct mode.
Each channel can be forced into the Full or Half Duplex
modes by either setting the duplex bit in the MI serial port
Control register or asserting the DPLX pin for the
corresponding channel with AutoNegotiation disabled.
The device can automatically configure itself for Full or
Half Duplex modes by using the AutoNegotiation algorithm
to advertise and detect Full and Half Duplex capabilities to
and from a remote terminal. For detailed information, refer
to the LINK INTEGRITY & AUTONEGOTIATION Section.
2.16.2 10 Mbps
Full Duplex in 10 Mbps mode is identical to the 100 Mbps
mode.
2.16.3 Full Duplex Indication
Full Duplex detect activity can be monitored through the
duplex detect bit in the MI serial port Channel Status
Output register.
Full Duplex detect activity also appears on the LED1 pin
by default.
2.17 10/100 MBPS SELECTION
2.17.1 General
The device can be forced into either the 100 or 10 Mbps
mode, or the device can detect 100 or 10 Mbps
capability from a remote device and automatically place
itself in the correct mode.
The device can be forced into either the 100 or 10 Mbps
mode by either setting the speed select bit in the MI serial
port Control register or by setting the SPEED pin with
AutoNegotiation disabled. Both the speed select bit and
SPEED pin need to be set to the same speed (10 or 100)
for the device to be properly configured. The speed select
bit and SPEED pin are ignored if AutoNegotiation is
enabled.
The device can automatically configure itself for 100 or 10
Mbps mode by using the AutoNegotiation algorithm to
advertise and detect 100 and 10 Mbps capabilities to and
from a remote device. Refer to the LINK INTEGRITY &
AUTONEGOTIATION Section for more details on
AutoNegotiation.
2.17.2 10/100 MBPS Indication
The device speed (100/10 Mbps) can be monitored
through the speed bit in the MI serial port Channel Status
Output register.
2.18 RESET
The 84221 is reset when either:
(1) VDD is applied to the device,
(2) the reset bit is set in the MI serial port Control
register, or
(3) the RESET pin is asserted active low.
When the reset is initiated by either (1) or (2), an internal
power-on reset pulse is generated which resets all internal
circuits, forces the MI serial port bits to their default
values, and latches in new values for the MI address. After
the power-on reset pulse has finished, the reset bit in the
MI serial port Control register is cleared and the device is
ready for normal operation. The device is guaranteed to
be ready for normal operation 50 mS after the reset was
initiated.
When the reset is initiated by (3), the identical procedure
takes place as in (1) and (2), except the device stays in
reset until the RESET pin is deasserted high.
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