參數(shù)資料
型號(hào)： 84221
英文描述： 84221 Quad 10/100 Mbps TX/FX/10BT (PHY) manual 1/99
中文描述： 84221四10/100 Mbps的TX/FX/10BT（PHY）的手冊(cè)1 / 99
文件頁數(shù)： 69/70頁
文件大?。?/td> 1017K
代理商： 84221
69
MD400184/A
84221
Ordering Information
Q
PACKAGE
TYPE
TEMPERATURE
RANGE
PART TYPE
Q – 0
°
C to +70
°
C
Quad 100 Base-TX/FX10 Base-T
Physical Layer Device (PHY)
84221
Q
Q = Plastic Quad
Flat Pack
Z
/
PRODUCT REV
This document is subject to changed without notice. SEEQ Technology Incorporated assumes no
responsibility for any errors contained herein.
Copyright by SEEQ Technology Incorporated, All Rights Reserved.
Revision History
99191
Document Revision changed to MD400184/A
Global: All references to FX or 100BaseFX have been deleted.
Page 16: Section 2.4.1 4B5B Decoder - 100 Mbps
- Paragraph #2 has had a copy change.
- Section 2.6.3 Scambler Bypass, has been deleted.
Page 17: Section 2.7.1 100 Mbps
- Paragraph #3 has been deleted.
- Section 2.7.3 has been deleted.
Page 19: Section 2.11.1 100 Mbps
- Paragraph #5 has had a copy change.
- Section 2.12.1 100 Mbps has had a copy change.
Page 32: Table 8. MI Serial Port Register Map
- 18 Channel Status Output , Bit X.14 is now 0, Bit X.9 and X.8 are now —, Bits X.3, X.2, X.1, X.0 are now 0.
Page 67: Figure 25. Jabber Timing
- Timing COL,and CRS have been deleted.
Page 41: Table 17. Register 18 - Channel Status Output Register Definition
- Bits 18.14, 18.9, 18.8, 18.3, 18.2, 18.1 are now blank.
- Definitions 18.14, 18.9, 18.8, 18.3, 18.2, 18.1, have been changed to Reserved.
- Symbol and name for 18.14, 18.9, 18.8, 18.3, 18.2, 18.1 are now blank.
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