
16
MD400184/A
84221
The Manchester encoding process is only done on actual
packet data, and the idle period between packets is not
Manchester encoded, but filled with link pulses.
2.4  DECODER
2.4.1 4B5B Decoder - 100 Mbps
Since the TX input data is 4B5B encoded on the transmit
side, it must also be decoded by the 4B5B decoder on the
receive side.   The mapping of the 5B nibbles to the 4B
code words is specified in IEEE 802.3 and shown in Table
2. The 84221 4B5B  decoder takes the 5B code words
from the descrambler, converts them into 4B nibbles per
Table 2, and sends the 4B nibbles to the RMII controller
interface. The 4B5B decoder also strips off the SSD
delimiter (/J/K/ symbols) and replaces them with two 4B
Data 5 nibbles  (/5/ symbol), and strips off the  ESD
delimiter (/T/R/ symbols) and replaces it with two 4B Data
0  nibbles (/I/ symbol), per IEEE 802.3 specifications and
shown in Figure 2.
The 4B5B decoder detects SSD, ESD and, codeword
errors in the incoming data stream as specified in IEEE
802.3.  These errors are indicated by asserting RXER
output while the errors are being transmitted across
RXD[1:0].
2.4.2 Manchester Decoder - 10 Mbps
In Manchester coded data,  the first half of the data bit
contains the complement of the data, and the second half
of the data bit contains the true data.  The 84221
Manchester decoder converts the single data stream from
the TP receiver into NRZ data for the controller interface
by decoding the data and stripping off the SOI pulse.
Since the clock and data recovery block has already
separated the clock and data from the TP receiver, the
Manchester decoding process to NRZ data is inherently
performed by that block.
2.5 CLOCK AND DATA RECOVERY
2.5.1 Clock Recovery - 100 Mbps
Clock recovery is done with a PLL.  If there is no valid data
present on the receive inputs, the PLL is locked to the
CLKIN clock.  When valid data is detected on the receive
inputs with the squelch circuit and when the adaptive
equalizer has settled, the PLL input is switched to the
incoming data stream.  The PLL then recovers a clock by
locking onto the transitions of the incoming signal.  The
recovered clock is output to the Controller Interface block.
2.5.2 Data Recovery - 100 Mbps
Data recovery is performed by latching in data from the
receive inputs with the recovered clock extracted by the
PLL.  
2.5.3 Clock Recovery - 10 Mbps
The clock recovery process for 10 Mbps mode is identical
to the 100 Mbps mode, except:
 The PLL is switched from CLKIN to the TP input when 
the squelch indicates valid data.
 The PLL  locks onto the preamble signal in less than 12 
transitions (bit times).
 Some of the preamble data symbols are lost while the 
PLL is locking onto the preamble, however,  the data 
receiver block recovers enough preamble symbols to 
pass at least 3 bytes of preamble to the controller 
interface as shown in Figure 3.
2.5.4 Data Recovery
The data recovery process for 10 Mbps mode is identical
to the 100 Mbps mode.
2.6 SCRAMBLER
2.6.1 100 Mbps
100BaseTX requires scrambling to reduce the radiated
emmisions on the twisted pair.  The 84221 scrambler
takes the encoded data from the 4B5B encoder,
scrambles it per the IEEE 802.3 specifications, and sends
it to the TP transmitter. The scrambler circuitry of the
84221 is designed so that none of the individual scrambler
sections on-chip will be synchronous with the others to
minimize EMI issues.
2.6.2 10 Mbps
A scrambler is not used in 10 Mbps mode.