參數(shù)資料
型號(hào)： 84221
英文描述： 84221 Quad 10/100 Mbps TX/FX/10BT (PHY) manual 1/99
中文描述： 84221四10/100 Mbps的TX/FX/10BT（PHY）的手冊(cè)1 / 99
文件頁(yè)數(shù)： 18/70頁(yè)
文件大?。?/td> 1017K
代理商： 84221
18
MD400184/A
84221
The 100 Mbps receiver consists of an adaptive equalizer,
baseline wander correction circuit, comparators, and MLT-
3 decoder. The TP inputs first go to an adaptive equalizer.
The adaptive equalizer compensates for the low pass
characteristic of the cable, and it has the ability to adapt
and compensate for 0-100 meters of category 5, 100 Ohm
UTP The baseline wander correction circuit restores the
DC component of the input waveform that was removed by
external transformers. The comparators convert the
equalized signal back to digital levels and are used to
qualify the data with the squelch circuit. The MLT-3
decoder takes the three level MLT-3 digital data from the
comparators and converts it back to normal digital data to
be used for clock and data recovery.
2.9.2 Receiver - 10 Mbps
The 10 Mbps mode receiver is much simpler than the 100
Mbps mode receiver and is identical to the 100 Mbps
receiver except:
The adaptive equalizer is disabled and bypassed.
The baseline wander correction circuit is disabled.
The 10 Mbps receiver is able to detect input signals
from the twisted pair cable that are within the template
specified in IEEE 802.3 Clause 14 and shown in Figure
5.
The output of the squelch comparator is used for
squelch, link pulse detect, SOI detect, reverse polarity
detect.
The data comparator is a zero crossing comparator
whose output is used for clock and data recovery.
2.9.3 Squelch - 100 Mbps
The squelch block determines whether the input contains
valid data. The 100 Mbps TX squelch is one of the criteria
used to determine link intergrity. The squelch comparators
compare the TX inputs against fixed positive and negative
thresholds, called squelch levels.
The output from the squelch comparator goes to a digital
squelch circuit, which determines whether the receive
input data on that channel is valid. If the data is invalid,
the receiver is in the squelched state. If the input voltage
exceeds the squelch levels at least four times with
alternating polarity within a 10 uS interval, the data is
considered to be valid by the squelch circuit and the
receiver now enters into the unsquelch state.
In the unsquelch state, the receive threshold level is
reduced by approximately 30% for noise immunity reasons
and is called the unsquelch level. When the receiver is in
the unsquelch state the input signal is considered valid.
The device stays in the unsquelch state until loss of data
is detected. Loss of data is detected if no alternating
polarity unsquelch transitions are detected during any
10 uS interval. When the loss of data is detected, the
receive squelch level is re-established.
2.9.4 Squelch - 10 Mbps
The TP squelch algorithm for 10 Mbps mode is identical
to the 100 Mbps mode, except:
The 10 Mbps squelch algorithm is not used for link
integrity, but to sense the beginning of a packet.
The receiver goes into the unsquelch state if the input
voltage exceeds the squelch levels for three bit times
with alternating polarity within a 50-250 nS interval.
The receiver goes into the squelch state when SOI is
detected.
Unsquelch detection has no affect on link integrity, link
pulses are used for that in 10 Mbps mode.
Start of packet is determined when the receiver goes
into the unsquelch state and CRS is asserted.
The receiver meets the squelch requirements defined in
IEEE 802.3 Clause 14.
2.9.5 Receive Level Adjust
The receiver squelch and unsquelch levels can be
lowered by 4.5 dB by setting the receive level adjust bit in
the MI serial port Channel Configuration register. By
setting this bit, the device can support cable lengths
exceeding 100 meters.
2.10 COLLISION
The collision function is not present in the 84221. The
MAC should be able to reliably detect collision based on
the TXEN and CRS_DV signals.
2.11 START OF PACKET
2.11.1 100 Mbps
Start of packet for 100 Mbps mode is indicated by a
unique Start of Stream Delimiter (SSD). The SSD pattern
consists of the two /J/K/ 5B symbols inserted at the
beginning of the packet in place of the first two preamble
symbols, as defined in IEEE 802.3 Clause 24 and shown
in Table 2 and Figure 2.
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