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| 型號： | 7643 |
| 英文描述： | IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE |
| 中文描述： | 7643Group數(shù)據(jù)表數(shù)據(jù)表1369K/JUL.30.03 |
| 文件頁數(shù)： | 91/120頁 |
| 文件大小： | 1369K |
| 代理商： | 7643 |
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Rev.1.00 Jul 30, 2003 page 91 of 119
7643 Group
Software Commands (CPU Rewrite Mode)
Table 21 lists the software commands.
After setting the CPU Rewrite Mode Select Bit of the flash memory
control register to “1”, execute a software command to specify an
erase or program operation.
Each software command is explained below.
●
Read Array Command (FF
16
)
The read array mode is entered by writing the command code
“FF
16
” in the first bus cycle. When an address to be read is input in
one of the bus cycles that follow, the contents of the specified ad-
dress are read out at the data bus (DB
0
to DB
7
).
The read array mode is retained intact until another command is
written.
●
Read Status Register Command (70
16
)
The read status register mode is entered by writing the command
code “70
16
” in the first bus cycle. The contents of the status regis-
ter are read out at the data bus (DB
0
to DB
7
) by a read in the
second bus cycle.
The status register is explained in the next section.
●
Clear Status Register Command (50
16
)
This command is used to clear the bits SR4 and SR5 of the status
register after they have been set. These bits indicate that opera-
tion has ended in an error. To use this command, write the
command code “50
16
” in the first bus cycle.
●
Program Command (40
16
)
Program operation starts when the command code “40
16
” is writ-
ten in the first bus cycle. Then, if the address and data to program
are written in the 2nd bus cycle, program operation (data program-
ming and verification) will start.
Whether the write operation is completed can be confirmed by
reading the status register or the RY/BY Status Flag of the flash
memory control register. When the program starts, the read status
Table 21 List of software commands (CPU rewrite mode)
register mode is entered automatically and the contents of the sta-
tus register is read at the data bus (DB
0
to DB
7
). The status
register bit 7 (SR7) is set to “0” at the same time the write opera-
tion starts and is returned to “1” upon completion of the write
operation. In this case, the read status register mode remains ac-
tive until the next command is written.
The RY/BY Status Flag is “0” (busy) during write operation and “1”
(ready) when the write operation is completed as is the status reg-
ister bit 7.
At program end, program results can be checked by reading bit 4
(SR4) of the status register.
Fig. 81 Program flowchart
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