參數(shù)資料
型號(hào): 7643
英文描述: IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE
中文描述: 7643Group數(shù)據(jù)表數(shù)據(jù)表1369K/JUL.30.03
文件頁數(shù): 68/120頁
文件大?。?/td> 1369K
代理商: 7643
Rev.1.00 Jul 30, 2003 page 68 of 119
7643 Group
HOLD Function
The HOLD function is used for systems that consist of external cir-
cuits that access MCU buses without use of the CPU (Central
Processing Unit). The HOLD function is used to generate the tim-
ing in which the MCU will relinquish the bus from the CPU to the
external circuits. To use the HOLD function, set the HOLD function
Enable Bit of CPU mode register B (address 0001
16
) to “1”. This
function can be used with both the HOLD pin and the HLDA pin.
The HOLD signal is a signal from an external circuit requesting the
MCU to relinquish use of the bus. When “L” level is input, the MCU
goes to the HOLD state and remains so while the pin is at “L”. The
oscillator does not stop oscillating during the HOLD state, there-
fore allowing the internal peripheral functions to operate during
this time.
When the MCU relinquishes use of the bus, “L” level is output from
the HLDA pin. The MCU makes ports P0 and P1 (address buses)
and port P2 (data bus) tri-state outputs and holds port P3
7
(RD
pin) and port P3
6
(WR pin) “H” level. Port P3
4
(
φ
OUT
pin) contin-
ues to oscillate. This function is not valid when the MCU is using
the IBF
1
function with the HLDA pin.
Expanded Data Memory Access
In Expanded Data Memory Access Mode, the MCU can access a
data area larger than 64 Kbytes with the LDA ($zz), Y (indirect Y)
instruction and the STA ($zz), Y (indirect Y) instruction.
To use this mode, set the Expanded Data Memory Access Bit of
CPU mode register B (address 0001
16
) to “1”. In this case, port
P4
0
(EDMA pin) goes “L” level during the read/write cycle of the
LDA or STA instruction.
The determination of which bank to access is done by using an I/
O port to represent expanded addresses exceeding address bus
AB
15
. For example, when accessing 4 banks, use two I/O ports to
represent address buses AB
16
and AB
17
.
Fig. 67 Hold function timing diagram
X
I
N
R
D
, W
R
A
D
D
R
O
U
T
D
A
T
A
I
N
/
O
U
T
H
O
L
D
H
L
D
A
φ
O
U
T
t
s
u
(
H
O
L
D
-
φ
)
t
h
(
φ
-
H
O
L
D
)
t
d
(
φ
-
H
L
D
A
L
)
t
d
(
φ
-
H
L
D
A
H
)
N
o
t
e
:
T
h
i
s
d
i
a
g
r
a
m
a
s
s
u
m
e
s
φ
=
X
I
N
/
2
.
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