參數(shù)資料
型號(hào)： 7643
英文描述： IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE
中文描述： 7643Group數(shù)據(jù)表數(shù)據(jù)表1369K/JUL.30.03
文件頁(yè)數(shù)： 50/120頁(yè)
文件大?。?/td> 1369K
代理商： 7643
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Rev.1.00 Jul 30, 2003 page 50 of 119
7643 Group
[USB Endpoint 0 IN Control Register ] IN_CSR
This register contains the control and status information of the
endpoint 0. This USB FCU sets the OUT_PKT_RDY flag to “1”
upon having received a data packet in the OUT FIFO. When read-
ing its one data packet from the OUT FIFO, be sure to set this flag
to “0”.
After a SETUP token is received, the MCU is in the “decode wait
state” until the OUT_PKT_RDY flag is cleared. If the
OUT_PKT_RDY flag is not cleared (indicating that the host re-
quest has not been successfully decoded), the USB FCU keep
returning a NAK to the host for all IN/OUT tokens.
Set the IN_PKT_RDY bit to “1” after the data packet has been
written to the IN FIFO. If this bit is set to “1” even though nothing
has been written to the IN FIFO, a “0” length data (NULL packet)
is sent to the host. The SEND_STALL bit is for sending a STALL to
the host if an unsupported request is received by the USB FCU.
This bit must be set to “1”. When the OUT_PKT_RDY flag is set to
“0” for request reception, the USB FCU transmits a STALL signal
to the Host CPU. Perform the following three processes simulta-
neously:
Set SEND_STALL bit to “1”
Set DATA_END bit to “1”
Set OUT_PKT_RDY flag to “0” by setting SERVICED_OUT
_PKT_RDY bit to “1”.
Note that if “0” is written to the SEND_STALL bit before the
CLEAR_FEATURE (endpoint STALL) request has been received,
the next STALL will not be generated.
The DATA_END bit informs the USB FCU of the completion of the
process indicated in the SETUP packet. Set this bit to “1” when
the process requested in the SETUP packet is completed. (Con-
trol Read Transfer: set this bit after writing all of the requested
data to the FIFO; Control Write Transfer: set this bit to “1” after
reading all of the requested data from the FIFO.) When this bit is
“1”, the host request is ignored and a STALL is returned. After the
status phase process is completed, the USB FCU automatically
clears it to “0”.
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Fig. 43 Structure of USB endpoint 0 IN control register
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