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參數(shù)資料
| 型號： | 7643 |
| 英文描述： | IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE |
| 中文描述： | 7643Group數(shù)據(jù)表數(shù)據(jù)表1369K/JUL.30.03 |
| 文件頁數(shù)： | 14/120頁 |
| 文件大?。?/td> | 1369K |
| 代理商： | 7643 |
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Rev.1.00 Jul 30, 2003 page 14 of 119
7643 Group
I/O PORTS
Direction Registers
The I/O ports P0–P8 have direction registers which determine the
input/output direction of each individual pin. Each bit in a direction
register corresponds to one pin, each pin can be set to be input port
or output port.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin becomes
an output pin.
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are float-
ing. If a pin set to input is written to, only the port output latch is
written to and the pin remains floating.
Slew Rate Control
By setting bits 0 to 5 of the port control register (address 0010
16
) to
“1”, slew rate control is enabled. VIHL or CMOS level can be used as
a port P2 input level.
Pull-up Control
By setting the port P2 pull-up control register (address 0012
16
), pull-
up of each pin of port P2 can be controlled with a program.
However, the contents of port P2 pull-up control register do not affect
ports programmed as the output ports but as the input ports.
Fig. 11 Structure of port control and port P2 pull-up control
registers
Port control register (address 0010
16
)
PTC
Port P0 to P3 slew rate control bit (
Note 1
)
0: Disabled
1: Enabled
Port P4 slew rate control bit (
Note 1
)
0: Disabled
1: Enabled
Port P5 slew rate control bit (
Note 1
)
0: Disabled
1: Enabled
Port P6 slew rate control bit (
Note 1
)
0: Disabled
1: Enabled
Port P7 slew rate control bit (
Note 1
)
0: Disabled
1: Enabled
Port P8 slew rate control bit (
Note 1
)
0: Disabled
1: Enabled
Port P2 input level select bit
0: Reduced VIHL level input (
Note 2
)
1: CMOS level input
Reserved bit (“0” at read/write)
Notes 1
: The slew rate function can reduce di/dt by modifying an internal
buffer structure.
2
: The characteristics of VIHL level is basically the same as that of
TTL level. But, its switching center point is a little higher than
TTL’s. Refer to section “Recommended operating conditions”.
b0
b7
0
Port P2 pull-up control register
(address 0012
16
) PUP2
b0
b7
Port P2
0
pull-up control bit
0: Disabled
1: Enabled
Port P2
1
pull-up control bit
0: Disabled
1: Enabled
Port P2
2
pull-up control bit
0: Disabled
1: Enabled
Port P2
3
pull-up control bit
0: Disabled
1: Enabled
Port P2
4
pull-up control bit
0: Disabled
1: Enabled
Port P2
5
pull-up control bit
0: Disabled
1: Enabled
Port P2
6
pull-up control bit
0: Disabled
1: Enabled
Port P2
7
pull-up control bit
0: Disabled
1: Enabled
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 764-3"x36yd-Red | 功能描述:膠帶 764 RED 3X36 YD BULK RoHS:否 制造商:3M Electronic Specialty 產(chǎn)品:Tapes 類型:Shielding 描述/功能:EMI/RFI Foil Shielding Tape 顏色: 材料:Copper Foil 寬度:1 in x 18 yds |
| 764-3"x36yd-White | 功能描述:膠帶 WHITE 3X36YD BULK RoHS:否 制造商:3M Electronic Specialty 產(chǎn)品:Tapes 類型:Shielding 描述/功能:EMI/RFI Foil Shielding Tape 顏色: 材料:Copper Foil 寬度:1 in x 18 yds |
| 764-3"x36yd-Yellow | 功能描述:膠帶 764 YELLOW 3X36 YD BULK RoHS:否 制造商:3M Electronic Specialty 產(chǎn)品:Tapes 類型:Shielding 描述/功能:EMI/RFI Foil Shielding Tape 顏色: 材料:Copper Foil 寬度:1 in x 18 yds |
| 7643_06 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:8-BIT SINGLE-CHIP MICROCOMPUTER |
| 76430 | 制造商:Brady Corporation 功能描述:TAPE, BARRICADE, BLACK/PHOSPHORESCENT, 2INX5YD; Tape Type:Safety, Hazard Warning; Tape Backing Material:Polyester Film; Tape Width - Metric:50.8mm; Tape Width - Imperial:2"; Tape Length - Metric:4.572m; Tape Length - Imperial:5yard ;RoHS Compliant: NA |
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