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參數(shù)資料
| 型號： | 7643 |
| 英文描述： | IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE |
| 中文描述： | 7643Group數(shù)據(jù)表數(shù)據(jù)表1369K/JUL.30.03 |
| 文件頁數(shù)： | 28/120頁 |
| 文件大?。?/td> | 1369K |
| 代理商： | 7643 |
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Rev.1.00 Jul 30, 2003 page 28 of 119
7643 Group
Serial I/O Normal Operation
The serial I/O counter is set to “7” by writing operation to the serial
I/O shift register (address 002A
16
). When the SRDY Output Select
bit is “1”, the SRDY pin goes “L” after that writing. On the negative
edge of the transfer clock the SRDY pin returns “H” and the data
of the first bit is transmitted from the STXD pin. The remaining
data are done from the STXD pin bit by bit on each falling edge of
the transfer clock.
Additionally, the data is latched from the SRXD pin on each rising
edge of the transfer clock and then the contents of the serial I/O
shift register are shifted by one bit.
When the internal system clock is selected as the transfer clock,
the followings occur at counting eight transfer clocks:
The serial I/O counter reaches “0”
The transfer clock halts at “H”
The serial I/O interrupt request bit is set to “1”
The STXD pin goes a high-impedance state after an 8-bit transfer
is completed.
When the external clock is selected as the transfer clock, the fol-
lowings occur at counting eight transfer clocks:
The serial I/O counter reaches “0”
The serial I/O interrupt request bit is set to “1”
In this case, the transfer clock needs to be controlled by the exter-
nal source because the transfer clock does not halt. Additionally,
the STXD pin does not go a high-impedance state after an 8-bit
transfer is completed.
Figure 23 shows serial I/O timing.
Fig. 23 Serial I/O timing
D
1
D
0
D
2
D
3
D
4
D
5
D
6
D
7
First
Last
STXD/SRXD
Synchronizing clock
SCLK (CPoL = 1, CPha =1 )
SCLK (CPoL = 0, CPha = 1)
SCLK (CPoL = 1, CPha = 0)
SCLK (CPoL = 0, CPha = 0)
●
Normal mode timing (LSB first)
Transfer clock
Synchronizing clock
Serial I/O shift
register write signal
SRDY signal
Serial I/O output STXD
Serial I/O input SRXD
(Note)
Interrupt request bit is set to “1”.
Note
: When the internal clock is selected as the transfer clock, the STXD pin goes to a high-impedance state after transfer completion.
●
SPI compatible mode timing
SRDY signal
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