參數(shù)資料
型號： 7643
英文描述： IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE
中文描述： 7643Group數(shù)據(jù)表數(shù)據(jù)表1369K/JUL.30.03
文件頁數(shù)： 80/120頁
文件大小： 1369K
代理商： 7643
Rev.1.00 Jul 30, 2003 page 80 of 119
7643 Group
φ
clock cycle time
φ
clock “H” pulse width
φ
clock “L” pulse width
AB
15
–AB
8
delay time
AB
15
–AB
8
valid time
AB
7
–AB
0
delay time
AB
7
–AB
0
valid time
WR delay time
WR valid time
RD delay time
RD valid time
SYNC
OUT
delay time
SYNC
OUT
valid time
DMA
OUT
delay time
DMA
OUT
valid time
RDY setup time
RDY hold time
HOLD setup time
HOLD hold time
HOLD “L” delay time
HOLD “H” delay time
Data bus setup time
Data bus hold time
Data bus delay time
Data bus valid time (
Note 1
)
EDMA delay time
EDMA valid time
WR pulse width
RD pulse width
AB
15
–AB
8
valid time before WR
AB
7
–AB
0
valid time before WR
AB
15
–AB
8
valid time after WR
AB
7
–AB
0
valid time after WR
AB
15
–AB
8
valid time before RD
AB
7
–AB
0
valid time before RD
AB
15
–AB
8
valid time after RD
AB
7
–AB
0
valid time after RD
RDY setup time before WR
RDY hold time after WR
RDY setup time before RD
RDY hold time after RD
Data bus setup time before RD
Data bus hold time after RD
Data bus delay time after WR
Data bus valid time after WR (
Note 1
)
EDMA delay time after WR
EDMA valid time after RD
USB output rise time, C
L
= 50 pF
USB output fall time, C
L
= 50 pF
t
C
(
φ
)
t
WH
(
φ
)
t
WL
(
φ
)
t
d
(
φ
-AH)
t
v
(
φ
-AH)
t
d
(
φ
-AL)
t
v
(
φ
-AL)
t
d
(
φ
-WR)
t
v
(
φ
-WR)
t
d
(
φ
-RD)
t
v
(
φ
-RD)
t
d
(
φ
-SYNC)
t
v
(
φ
-SYNC)
t
d
(
φ
-DMA)
t
v
(
φ
-DMA)
t
su
(RDY-
φ
)
t
h
(
φ
-RDY)
t
su
(HOLD-
φ
)
t
h
(
φ
-HOLD)
t
d
(
φ
-HLDAL)
t
d
(
φ
-HLDAH)
t
su
(DB-
φ
)
t
h
(
φ
-DB)
t
d
(
φ
-DB)
t
V
(
φ
-DB)
t
d
(
φ
-EDMA)
t
v
(
φ
-EDMA)
t
WL
(WR) (
Note 2
)
t
WL
(RD) (
Note 2
)
t
d
(AH-WR)
t
d
(AL-WR)
t
v
(WR-AH)
t
v
(WR-AL)
t
d
(AH-RD)
t
d
(AL-RD)
t
v
(RD-AH)
t
v
(RD-AL)
t
su
(RDY-WR)
t
h
(WR-RDY)
t
su
(RDY-RD)
t
h
(RD-RDY)
t
su
(DB-RD)
t
h
(RD-DB)
t
d
(WR-DB)
t
v
(WR-DB)
t
v
(WR-EDMA)
t
v
(RD-EDMA)
t
r
(D+), t
r
(D-)
t
f
(D+), t
f
(D-)
Limits
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Min.
166.66
0.5tc(
φ
) – 5
0.5tc(
φ
) – 5
0
0
0
0
0
0
35
0
21
0
9
0
15
0
0.5tc(
φ
) – 6
0.5tc(
φ
) – 6
0.5tc(
φ
) – 33
0.5tc(
φ
) – 35
0
0
0.5tc(
φ
) – 33
0.5tc(
φ
) – 35
0
0
45
0
45
0
18
0
12
0
0
4
4
Typ.
Max.
Symbol
Unit
Table 19 Timing requirements and switching characteristics in memory expansion and microprocessor modes
(Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted)
45
47
8
8
11
26
In Vcc = 3 V
30
30
30
15
28
20
20
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