參數資料
型號： 7643
英文描述： IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE
中文描述： 7643Group數據表數據表1369K/JUL.30.03
文件頁數： 37/120頁
文件大?。?/td> 1369K
代理商： 7643
Rev.1.00 Jul 30, 2003 page 37 of 119
7643 Group
DMAC index and status register (address 003F
16
)
DMAIS
DMAC channel 0 count register underflow flag (D0UF)
0: No underflow
1: Underflow generated
DMAC channel 0 suspend flag (D0SFI)
0: Not suspended
1: Suspended
DMAC channel 1 count register underflow flag (D1UF)
0: No underflow
1: Underflow generated
DMAC channel 1 suspend flag (D1SFI)
0: Not suspended
1: Suspended
DMAC transfer suspend control bit (DTSC)
0: Suspending only burst transfers during interrupt
process
1: Suspending both burst and cycle steal transfers
during interrupt process
DMAC register reload disable bit (DRLDD)
0: Enabling reload of source and destination registers
of both channels
1: Disabling reload of source and destination registers
of both channels
Reserved bit (“0” at read/write)
Channel index bit (DCI)
0: Channel 0 accessible
1: Channel 1 accessible
DMAC channel x mode register 1 (address 0040
16
)
DMAxM1
DMAC channel x source register increment/decrement
selection bit (DxSRID)
0: Increment after transfer
1: Decrement after transfer
DMAC channel x source register increment/decrement enable
bit (DxSRCE)
0: Increment/Decrement disabled (No change after transfer)
1: Increment/Decrement enabled
DMAC channel x destination register increment/decrement
selection bit (DxDRID)
0: Increment after transfer
1: Decrement after transfer
DMAC channel x destination register increment/decrement
enable bit (DxDRCE)
0: Increment/Decrement disabled (No change after transfer)
1: Increment/Decrement enabled
DMAC channel x data write control bit (DxDWC)
0: Writing data in reload latches and registers
1: Writing data in reload latches only
DMAC channel x disable after count register underflow
enable bit (DxDAUE)
0: Channel x enabled after count register underflow
1: Channel x disabled after count register underflow
DMAC channel x register reload bit (DxRLD)
0: Not reloaded (Bit is always read as “0”)
1: Source, destination, and transfer count registers contents
of channel x to be reloaded
DMAC channel x transfer mode selection bit (DxTMS)
0: Cycle steal transfer mode
1: Burst transfer mode
DMAC channel 0 hardware transfer request source bits (D0HR)
b3b2b1b0
0 0 0 0: Not used
0 0 0 1: UART receive interrupt
0 0 1 0: UART transmit interrupt
0 0 1 1: Not used
0 1 0 0: INT
0
interrupt
0 1 0 1: USB endpoint 1 IN_PKT_RDY signal
(falling edge active)
0 1 1 0: USB endpoint 2 IN_PKT_RDY signal
(falling edge active)
0 1 1 1: Not used
1 0 0 0: USB endpoint 1 OUT_PKT_RDY signal
(rising edge active)
1 0 0 1: USB endpoint 1 OUT_FIFO_NOT_EMPTY signal
(rising edge active)
1 0 1 0: USB endpoint 2 OUT_PKT_RDY signal
(rising edge active)
1 0 1 1: Not used
1 1 0 0: Not used
1 1 0 1: Not used
1 1 1 0: Serial I/O trasmit/receive interrupt
1 1 1 1: Not used
DMAC channel 0 software transfer trigger (D0SWT)
0: No action (Bit is always read as “0”)
1: Request of channel 0 transfer by writing “1” (
Note 1
)
Reserved bit (“0” at read/write)
DMAC channel 0 transfer initiation source capture
register reset bit (D0CRR)
0: No action (Bit is always read as “0”)
1: Reset of channel 0 capture register by writing “1” (
Note 1
)
DMAC channel 0 enable bit (D0CEN)
0: Channel 0 disabled
1: Channel 0 enabled (
Note 2
)
DMAC channel 0 mode register 2 (address 0041
16
)
DMA0M2
DMAC channel 1 hardware transfer request source bits (D1HR)
b3b2b1b0
0 0 0 0: Not used
0 0 0 1: Not used
0 0 1 0: Not used
0 0 1 1: Not used
0 1 0 0: INT
1
interrupt
0 1 0 1: USB endpoint 1 IN_PKT_RDY signal
(falling edge active)
0 1 1 0: USB endpoint 2 IN_PKT_RDY signal
(falling edge active)
0 1 1 1: Not used
1 0 0 0: USB endpoint 1 OUT_PKT_RDY signal
(rising edge active)
1 0 0 1: USB endpoint 1 OUT_FIFO_NOT_EMPTY signal
(rising edge active)
1 0 1 0: USB endpoint 2 OUT_PKT_RDY signal
(rising edge active)
1 0 1 1: Not used
1 1 0 0: Not used
1 1 0 1: Not used
1 1 1 0: Timer 1 trasmit/receive interrupt
1 1 1 1: Not used
DMAC channel 1 software transfer trigger (D1SWT)
0: No action (Bit is always read as “0”)
1: Request of channel 0 transfer by writing “1” (
Note 1
)
Reserved bit (“0” at read/write)
DMAC channel 1 transfer initiation source capture
register reset bit (D1CRR)
0: No action (Bit is always read as “0”)
1: Reset of channel 1 capture register by writing “1” (
Note 1
)
DMAC channel 1 enable bit (D1CEN)
0: Channel 0 disabled
1: Channel 0 enabled (
Note 2
)
DMAC channel 1 mode register 2 (address 0041
16
)
DMA1M2
b0
b7
b0
b7
b0
b7
b0
b7
Notes 1
: This bit is automatically cleared to “0” after writing “1”.
2
: When setting this bit to “1”, simultaneously set the DMAC channel x transfer initiation source capture register reset bit (bit 6 of DMAxM2) to “1”.
0
0
0
Fig. 30 Structure of DMACx related register
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相關代理商/技術參數
參數描述
764-3"x36yd-Red 功能描述:膠帶 764 RED 3X36 YD BULK RoHS:否 制造商:3M Electronic Specialty 產品:Tapes 類型:Shielding 描述/功能:EMI/RFI Foil Shielding Tape 顏色: 材料:Copper Foil 寬度:1 in x 18 yds
764-3"x36yd-White 功能描述:膠帶 WHITE 3X36YD BULK RoHS:否 制造商:3M Electronic Specialty 產品:Tapes 類型:Shielding 描述/功能:EMI/RFI Foil Shielding Tape 顏色: 材料:Copper Foil 寬度:1 in x 18 yds
764-3"x36yd-Yellow 功能描述:膠帶 764 YELLOW 3X36 YD BULK RoHS:否 制造商:3M Electronic Specialty 產品:Tapes 類型:Shielding 描述/功能:EMI/RFI Foil Shielding Tape 顏色: 材料:Copper Foil 寬度:1 in x 18 yds
7643_06 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:8-BIT SINGLE-CHIP MICROCOMPUTER
76430 制造商:Brady Corporation 功能描述:TAPE, BARRICADE, BLACK/PHOSPHORESCENT, 2INX5YD; Tape Type:Safety, Hazard Warning; Tape Backing Material:Polyester Film; Tape Width - Metric:50.8mm; Tape Width - Imperial:2"; Tape Length - Metric:4.572m; Tape Length - Imperial:5yard ;RoHS Compliant: NA
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