參數(shù)資料
型號: 7643
英文描述: IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE
中文描述: 7643Group數(shù)據(jù)表數(shù)據(jù)表1369K/JUL.30.03
文件頁數(shù): 32/120頁
文件大?。?/td> 1369K
代理商: 7643
Rev.1.00 Jul 30, 2003 page 32 of 119
7643 Group
UTXD output (P8
4
/UTXD)
D
0
D
1
SP
ST
D
2
D
3
D
4
D
5
D
6
D
7
P
SP
Transfer clock
Tranmit enable bit
Transmit buffer
empty flag
Transmit complete flag
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
ST
P
D
0
D
1
ST
Data set into UART transmit buffer register 1
Data transferring from UART transmit
buffer register 1 to Transmit shift register 1
This timing applies to the conditions:
Character length = 8 bits
Parity enabled
1 stop bit
RTS (Request-to-Send) Function
As a receiver, the UART can be configured to generate the Re-
quest-to-Send (RTS) handshaking signal. This is enabled by
setting the RTS Function Enable Bit (bit 6 of UCON) to “1”.
When reception is enabled, that is the Receive Enable Bit is “1”,
the RTS pin goes “L” to inform a transmitter that reception is pos-
sible. The RTS pin goes “H” at reception starting and does “L” at
receiving of the last bit.
The delay time from the reception of the last stop bit to the asser-
tion of RTS is selectable using the RTS Assertion Delay Count
Select Bits.
BRG count source
D
0
URXD (P8
5
/URXD)
ST
SP
D
1
D
7
RTS pin (P8
7
/RTS)
Receive enable bit
Receive buffer
empty flag
Transfer clock
Transfer clock generated at falling edge
of start bit and receive started
Receive data latched
Data transferring from UART receive register 1
to Receive buffer register 1 (
Note
)
Note:
When no RTS assertion delay, the RTS pin goes “L”.
The RTS assertion delay counts are selected by bits 4 to 7 of UART RTS control register.
This timing applies to the conditions:
Character length = 8 bits
Parity enabled
1 stop bit
Fig. 26 UART transmit timing (CTS function disbled)
When the Receive Enable Bit is set to “0” or the Receive initializa-
tion bit is set to “1”, the RTS pin goes “H”. Even when the Receive
Enable Bit is set to “1”, the RTS pin goes “H” if detecting an invalid
start bit.
Figure 27 shows the UART receive timing.
Fig. 27 UART receiving timing (RTS function enabled)
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PDF描述
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765-11E 8 BIT INPUT/OUTPUT EXPANDER, I2C INTERFACE, -40C to +125C, 20-QFN, TUBE
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