
Operating Modes
Background Debug Mode
MC68HC912DG128 — Rev 3.0
Technical Data
MOTOROLA
Operating Modes
79
In special single-chip mode, BDM is enabled and active immediately out
of reset. BDM is available in all other operating modes, but must be
enabled before it can be activated. BDM should not be used in special
peripheral mode because of potential bus conflicts.
Once enabled, background mode can be made active by a serial
command sent via the BKGD pin or execution of a CPU12 BGND
instruction. While background mode is active, the CPU can interpret
special debugging commands, and read and write CPU registers,
peripheral registers, and locations in memory.
While BDM is active, the CPU executes code located in a small on-chip
ROM mapped to addresses $FF20 to $FFFF, and BDM control registers
are accessible at addresses $FF00 to $FF06. The BDM ROM replaces
the regular system vectors while BDM is active. While BDM is active, the
user memory from $FF00 to $FFFF is not in the map except through
serial BDM commands.
The MODE register controls the MCU operating mode and various
configuration options. This register is not in the map in peripheral mode
SMODN, MODB, MODA — Mode Select Special, B and A
These bits show the current operating mode and reflect the status of
the BKGD, MODB and MODA input pins at the rising edge of reset.
SMODN is Read anytime. May only be written in special modes
(SMODN = 0). The first write is ignored;
Bit 7
6
5
4
3
2
1
Bit 0
SMODN
MODB
MODA
ESTR
IVIS
EBSWAI
0
EME
RESET:
0
0
0
1
1
0
0
1
Special Single Chip
RESET:
0
0
1
1
1
0
0
1
Special Exp Nar
RESET:
0
1
0
1
1
0
0
1
Peripheral
RESET:
0
1
1
1
1
0
0
1
Special Exp Wide
RESET:
1
0
0
1
0
0
0
0
Normal Single Chip
RESET:
1
0
1
1
0
0
0
0
Normal Exp Nar
RESET:
1
1
1
1
0
0
0
0
Normal Exp Wide
MODE
— Mode Register
$000B
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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