Electrical Specifications
Technical Data
MC68HC912DG128 — Rev 3.0
390
Electrical Specifications
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MOTOROLA
Table 19-6. Analog Converter Characteristics (Operating)
V
DD
=
5.0 Vdc
±
10%, V
SS
=
0 Vdc, T
A
=
T
L
to T
H
, ATD Clock
=
2 MHz, unless otherwise noted
Characteristic
Symbol
Min
Typical
Max
Unit
8-bit resolution
(1)
1 count
20
mV
8-bit differential non-linearity
(2)
DNL
0.5
+
0.5
count
8-bit integral non-linearity
(2)
INL
1
+
1
count
8-bit absolute error
,(3)
2, 4, 8, and 16 ATD sample clocks
AE
1
+
1
count
10-bit resolution
(1)
1 count
5
mV
10-bit differential non-linearity
(2)
DNL
–2
2
count
10-bit integral non-linearity
(2)
INL
–2
2
count
10-bit absolute error
(3)
2, 4, 8, and 16 ATD sample clocks
AE
–2.5
2.5
count
Maximum source impedance
R
S
20
See
note
(4)
K
1. V
RH
V
RL
≥
5.12V; V
DDA
V
SSA
=
5.12V
2. At V
REF
= 5.12V, one 8-bit count = 20 mV, and one 10-bit count = 5mV.
INL and DNL are characterized using the process window parameters affecting the ATD accuracy, but they are not tested.
3. These values include quantization error which is inherently 1/2 count for any A/D converter.
4. Maximum source impedance is application-dependent. Error resulting from pin leakage depends on junction leakage into
the pin and on leakage due to charge-sharing with internal capacitance.
Error from junction leakage is a function of external source impedance and input leakage current. Expected error in result
value due to junction leakage is expressed in voltage (V
ERRJ
):
V
ERRJ
=
R
S
×
I
OFF
where I
OFF
is a function of operating temperature. Charge-sharing effects with internal capacitors are a function of ATD clock
speed, the number of channels being scanned, and source impedance. Charge pump leakage is computed as follows:
V
ERRJ
=
.25pF
×
V
DDA
×
R
S
×
ATDCLK/(8
×
number of channels)
F
Freescale Semiconductor, Inc.
n
.