Clock Functions
Limp-Home and Fast STOP Recovery modes
MC68HC912DG128 — Rev 3.0
Technical Data
MOTOROLA
Clock Functions
173
11.6.14 PLL Register Descriptions
Read anytime, write anytime, except when BCSP = 1 (PLL selected as
bus clock).
If the PLL is on, the count in the loop divider (SYNR) register effectively
multiplies up the bus frequency from the PLL reference frequency by
SYNR + 1. Internally, SYSCLK runs at twice the bus frequency. Caution
should be used not to exceed the maximum rated operating frequency
for the CPU.
Table 11-2. Summary of Pseudo STOP Mode Exit Conditions
Mode
Conditions
Summary
Pseudo-STOP exit in Limp Home
mode with Delay
NOLHM=0
CME=X
DLY=1
CPU exits stop in limp home mode and oscillator running. If
the oscillator fails during pseudo-STOP and then recovers
there is a possibility of code runaway as the
clock monitor
circuit can be misled by EXTALi clock into reporting a
good signal before it has fully stabilised
Pseudo-STOP exit
in Limp Home mode without
Delay (Fast Stop Recovery)
NOLHM=0
CME=X
DLY=0
This mode is not recommended as it is possible that the
initial VCO clock frequency may be high enough to cause
code runaway.
Pseudo-STOP exit without Limp
Home mode, clock monitor
enabled
NOLHM=1
CME=1
DLY=X
When a STOP instruction is executed the MCU resets via
the clock monitor reset vector.
Pseudo-STOP exit without Limp
Home mode, clock monitor
disabled, with Delay
NOLHM=1
CME=0
DLY=1
Oscillator starts operation following 4096 XCLK cycles
(actual controlled by SLOW mode divider).
Pseudo-STOP exit without Limp
Home mode, clock monitor
disabled, without Delay
NOLHM=1
CME=0
DLY=0
This mode is only recommended for use with an external
clock source.
Bit 7
6
5
4
3
2
1
Bit 0
0
0
SYN5
SYN4
SYN3
SYN2
SYN1
SYN0
RESET:
0
0
0
0
0
0
0
0
SYNR
— Synthesizer Register
$0038
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Freescale Semiconductor, Inc.
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