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參數(shù)資料
| 型號： | 5962-9205805QXA |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 32-BIT, 60 MHz, OTHER DSP, CPGA141 |
| 封裝： | STAGGERED, CERAMIC, PGA-141 |
| 文件頁數(shù)： | 30/54頁 |
| 文件大小： | 1033K |
| 代理商： | 5962-9205805QXA |
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026G APRIL 1998 REVISED SEPTEMBER 2006
36
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
serial-port timing for SMJ320C31-60 (see Figure 26 and Figure 27)
NO.
’C31-60
UNIT
NO.
MIN
MAX
UNIT
54
td(H1H-SCK)
Delay time, H1 high to internal CLKX/R
8
ns
55
tc(SCK)
Cycle time, CLKX/R
CLKX/R ext
tc(H)x2.6
ns
55
tc(SCK)
Cycle time, CLKX/R
CLKX/R int
tc(H)x2
tc(H)x232
ns
56
tw(SCK)
Pulse duration, CLKX/R high/low
CLKX/R ext
tc(H)+10
ns
56
tw(SCK)
Pulse duration, CLKX/R high/low
CLKX/R int
[tc(SCK)/2]5
[tc(SCK)/2]+5
ns
57
tr(SCK)
Rise time, CLKX/R
5
ns
58
tf(SCK)
Fall time, CLKX/R
5
ns
59
td(C-DX)
Delay time, CLKX to DX valid
CLKX ext
20
ns
59
td(C-DX)
Delay time, CLKX to DX valid
CLKX int
15
ns
60
tsu(DR-CLKRL)
Setup time, DR before CLKR low
CLKR ext
8
ns
60
tsu(DR-CLKRL)
Setup time, DR before CLKR low
CLKR int
15
ns
61
th(CLKRL-DR)
Hold time, DR from CLKR low
CLKR ext
6
ns
61
th(CLKRL-DR)
Hold time, DR from CLKR low
CLKR int
0
ns
62
td(C-FSX)
Delay time, CLKX to internal FSX high/low
CLKX ext
20
ns
62
td(C-FSX)
Delay time, CLKX to internal FSX high/low
CLKX int
14
ns
63
tsu(FSR-CLKRL)
Setup time, FSR before CLKR low
CLKR ext
6
ns
63
tsu(FSR-CLKRL)
Setup time, FSR before CLKR low
CLKR int
6
ns
64
th(SCKL-FS)
Hold time, FSX/R input from CLKX/R low
CLKX/R ext
6
ns
64
th(SCKL-FS)
Hold time, FSX/R input from CLKX/R low
CLKX/R int
0
ns
65
tsu(FSX-C)
Setup time, external FSX before CLKX
CLKX ext
[tc(H) 8]*
[tc(SCK)/2] 10*
ns
65
tsu(FSX-C)
Setup time, external FSX before CLKX
CLKX int
[tc(H) 21]*
tc(SCK)/2*
ns
66
td(CH-DX)V
Delay time, CLKX to first DX bit, FSX
CLKX ext
20*
ns
66
td(CH-DX)V
Delay time, CLKX to first DX bit, FSX
precedes CLKX high
CLKX int
12*
ns
67
td(FSX-DX)V
Delay time, FSX to first DX bit, CLKX precedes FSX
20*
ns
68
td(CH-DXZ)
Delay time, CLKX high to DX high impedance following last
data bit
12*
ns
* This parameter is not production tested.
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相關代理商/技術參數(shù) |
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|---|---|
| 5962-9205805QYA | 制造商:Texas Instruments 功能描述:DSP FLOATING PT 32BIT 60MHZ 30MIPS 132CFPAK - Rail/Tube |
| 596292062012MYC | 制造商:ALTERA 功能描述:EPM5192GM883B |
| 5962-92062012MYC | 制造商:ALTERA 功能描述:EPM5192GM883B |
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| 5962-9206202MYC | 制造商:e2v Aerospace & Defense 功能描述:CPLD, UV ERASABLE, 192-MACROCELL, 30 NS PROP. DELAY TIME |
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