參數(shù)資料
型號: 5962-9205805QXA
廠商: TEXAS INSTRUMENTS INC
元件分類: 數(shù)字信號處理
英文描述: 32-BIT, 60 MHz, OTHER DSP, CPGA141
封裝: STAGGERED, CERAMIC, PGA-141
文件頁數(shù): 17/54頁
文件大?。?/td> 1033K
代理商: 5962-9205805QXA
SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026G APRIL 1998 REVISED SEPTEMBER 2006
24
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
XF0 timing when executing STFI and STII
The following table defines the timing parameters for the XF0 pin during execution of STFI or STII.
timing for XF0 when executing STFI or STII (see Figure 18)
NO.
’C31-40
’LC31-40
’C31-50
’C31-60
UNIT
NO.
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
28
td(H3H-XF0H)
Delay time, H3 high to XF0 high
13
12
11
ns
XF0 is always set high at the beginning of the execute phase of the interlock-store instruction. When no pipeline conflicts occur, the address of
the store is also driven at the beginning of the execute phase of the interlock-store instruction. However, if a pipeline conflict prevents the store
from executing, the address of the store will not be driven until the store can execute.
H3
H1
STRB
R/W
A
D
RDY
XF0 Pin
Fetch
STFI or STII
Read
Execute
28
Decode
Figure 18. Timing for XF0 When Executing an STFI or STII
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