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參數(shù)資料
| 型號(hào)： | 5962D0053605QYX |
| 元件分類： | SRAM |
| 英文描述： | 512K X 8 STANDARD SRAM, 20 ns, CDFP36 |
| 封裝： | CERAMIC, DFP-36 |
| 文件頁(yè)數(shù)： | 1/16頁(yè) |
| 文件大?。?/td> | 138K |
| 代理商： | 5962D0053605QYX |
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1
FEATURES
20ns maximum (5 volt supply) address access time
Asynchronous operation for compatibility with industry-
standard 512K x 8 SRAMs
TTL compatible inputs and output levels, three-state
bidirectional data bus
Operational environment:
- Total dose: 50 krads(Si)
- SEL Immune 110 MeV-cm2/mg
- SEU LETTH(0.25) = 52 cm
2 MeV
- Saturated Cross Section 2.8E-8 cm2/bit
-<1.1E-9 errors/bit-day, Adams 90% worst case
environment geosynchronous orbit
Packaging:
- 36-lead ceramic flatpack (3.831 grams)
Standard Microcircuit Drawing 5962-00536
- QML Q and V compliant part
INTRODUCTION
The UT9Q512E RadTol product is a high-performance CMOS
static RAM organized as 524,288 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (E), an
active LOW Output Enable (G), and three-state drivers.
Writing to the device is accomplished by taking Chip Enable (E)
input LOW and Write Enable (W) inputs LOW. Data on the eight
I/O pins (DQ0 through DQ7) is then written into the location
specified on the address pins (A0 through A18). Reading from
the device is accomplished by taking Chip Enable (E) and
Output Enable (G) LOW while forcing Write Enable (W) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (DQ0 through DQ7) are placed in a
high impedance state when the device is deselected (E HIGH),
the outputs are disabled (G HIGH), or during a write operation
(E LOW and W LOW).
Standard Products
UT9Q512E 512K x 8 RadTol SRAM
Data Sheet
September, 2008
Memory Array
1024 Rows
512x8 Columns
Pre-Charge Circuit
Clk. Gen.
Row
Select
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
I/O Circuit
Column Select
Data
Control
CLK
Gen.
A10
A1
1
A12
A13
A14
A15
A16
A17
A18
DQ 0 - DQ 7
W
G
E
Figure 1. UT9Q512E SRAM Block Diagram
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