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參數(shù)資料
| 型號： | 5962D0053605QYX |
| 元件分類： | SRAM |
| 英文描述： | 512K X 8 STANDARD SRAM, 20 ns, CDFP36 |
| 封裝： | CERAMIC, DFP-36 |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 138K |
| 代理商： | 5962D0053605QYX |
8
AC CHARACTERISTICS WRITE CYCLE (Pre/Post-Radiation)*
-55
°C to +125°C for (C) screening and -40oC to +125oC for (E) screening (V
DD = 5.0V + 10%)
Notes:
* Post-radiation performance guaranteed at 25
°C per MIL-STD-883 Method 1019.
1. Functional test performed with outputs disabled (G high).
2. Three-state is defined as 500mV change from steady-state output voltage (see Figure 3).
SYMBOL
PARAMETER
9Q512-25
5.0V
MIN
MAX
UNIT
tAVAV
1
Write cycle time
20
ns
tETWH
Chip Enable to end of write
20
ns
tAVET
Address setup time for write (E - controlled)
0
ns
tAVWL
Address setup time for write (W - controlled)
0
ns
tWLWH
Write pulse width
20
ns
tWHAX
Address hold time for write (W - controlled)
2
ns
tEFAX
Address hold time for Chip Enable (E - controlled)
0
ns
tWLQZ
2
W - controlled three-state time
10
ns
tWHQX
W - controlled Output Enable time
4
ns
tETEF
Chip Enable pulse width (E - controlled)
20
ns
tDVWH
Data setup time
15
ns
tWHDX
Data hold time
2
ns
tWLEF
Chip Enable controlled write pulse width
20
ns
tDVEF
Data setup time
15
ns
tEFDX
Data hold time
2
ns
tAVWH
Address valid to end of write
20
ns
tWHWL
1
Write disable time
5
ns
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