參數(shù)資料
型號: 5962-9205805QXA
廠商: TEXAS INSTRUMENTS INC
元件分類: 數(shù)字信號處理
英文描述: 32-BIT, 60 MHz, OTHER DSP, CPGA141
封裝: STAGGERED, CERAMIC, PGA-141
文件頁數(shù): 16/54頁
文件大?。?/td> 1033K
代理商: 5962-9205805QXA
SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026G APRIL 1998 REVISED SEPTEMBER 2006
23
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
XF0 and XF1 timing when executing LDFI or LDII
The following table defines the timing parameters for XF0 and XF1 during execution of LDFI or LDII.
timing for XF0 and XF1 when executing LDFI or LDII for SMJ320C31 (see Figure 17)
NO.
’C31-40
’LC31-40
’C31-50
’C31-60
UNIT
NO.
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
25
td(H3H-XF0L)
Delay time, H3 high to XF0 low
13
12
11
ns
26
tsu(XF1-H1L)
Setup time, XF1 before H1 low
9
10
8
ns
27
th(H1L-XF1)
Hold time, XF1 after H1 low
0
ns
H3
H1
STRB
R/W
A
D
RDY
XF0 Pin
XF1 Pin
Fetch
LDFI or LDII
Decode
Read
Execute
25
26
27
Figure 17. Timing for XF0 and XF1 When Executing LDFI or LDII
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