參數(shù)資料
型號(hào): 5962-9205805QXA
廠商: TEXAS INSTRUMENTS INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 32-BIT, 60 MHz, OTHER DSP, CPGA141
封裝: STAGGERED, CERAMIC, PGA-141
文件頁數(shù): 22/54頁
文件大?。?/td> 1033K
代理商: 5962-9205805QXA
SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026G APRIL 1998 REVISED SEPTEMBER 2006
29
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
RESET timing (see Figure 23)
NO.
’C31-40
’LC31-40
’C31-50
’C31-60
UNIT
NO.
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
38
tsu(RESET-CIL)
Setup time, RESET before
CLKIN low
10
P*
10
P*
10
P*
7
P*
ns
39
td(CLKINH-H1H)
Delay time, CLKIN high to
H1 high (see Note 4)
2
14
2
14
2
10
2
10
ns
40
td(CLKINH-H1L)
Delay time, CLKIN high to
H1 low (see Note 4)
2
14
2
14
2
10
2
10
ns
41
tsu(RESETH-H1L)
Setup time, RESET high
before H1 low and after ten
H1 clock cycles
9
7
6
ns
42
td(CLKINH-H3L)
Delay time, CLKIN high to
H3 low (see Note 4)
2
14
2
14
2
10
2
10
ns
43
td(CLKINH-H3H)
Delay time, CLKIN high to
H3 high (see Note 4)
2
14
2
14
2
10
2
10
ns
44
tdis(H1H-DZ)
Disable time, H1 high to D
(high impedance)
15*
13*
12*
11*
ns
45
tdis(H3H-AZ)
Disable time, H3 high to A
(high impedance)
9*
8*
7*
ns
46
td(H3H-CONTROLH)
Delay time, H3 high to
control signals high
9*
8*
7*
ns
47
td(H1H-RWH)
Delay time, H1 high to R/W
high
9*
8*
7*
ns
48
td(H1H-IACKH)
Delay time, H1 high to IACK
high
9*
8*
7*
ns
49
tdis(RESETL-ASYNCH)
Disable time, RESET low to
asynchronous reset signals
disabled (high impedance)
21*
17*
14*
ns
P = tc(CI)
* This parameter is not production tested.
NOTE 4: See Figure 12 and Figure 13 for typical temperature dependence.
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