參數(shù)資料
型號(hào)： 4565B2
廠商： LSI CORP
元件分類： 數(shù)字傳輸電路
英文描述： ATM/SONET/SDH SUPPORT CIRCUIT, PBGA909
封裝： PLASTIC, BGA-909
文件頁(yè)數(shù)： 53/61頁(yè)
文件大小： 1691K
代理商： 4565B2
Hardware Design Guide, Revision 2
4565B Ultramapper Full Transport Retiming Device
December 17, 2003
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
Agere Systems Inc.
57
Table 7-4. Microprocessor Interface Asynchronous Read Cycle Specifications
Symbol
Parameter
Setup
(Min)
Hold
(Min)
Delay
(Min)
Delay
(Max)
Unit
tCSFDSF
CSN Fall Setup and Hold to DSN Fall
0
—*
* CSN must be held low (active) until ADSN and DSN are deasserted.
——
ns
tAICSR
CSN Rise to ADDR Invalid
—
0
—
ns
tAVADSF
ADDR Valid Setup and Hold to ADSN Fall
1.0
—
ADDR must be held constant while ADSN and DSN are valid (low).
——
ns
tADSRAI
ADSN Rise to ADDR Invalid
—
1.4
—
ns
tAVDSF
ADDR Valid Setup and Hold to DSN Fall
0
—
——
ns
tDSNRAI
DSN Rise to ADDR Invalid
—
0
—
ns
tCSFDTR
CSN Fall to DTN Rise
—
5.2
16.0
ns
tDSFDTF
DSN Fall to DTN Fall
—
0
—
—
DTN fall is variable, depending on the block selected for access and in some cases, the state of the SONET frame. This interval is typically in the
100 ns to 200 ns range, but can be several hundred ns. In lab measurements, it has never exceeded 1000 ns. Certain registers in the VTMPR
block have a very long acknowledge cycle (in the order of 32 MPCLK cycles). The reason for this is that those registers can also be accessed by
the VTMPR lower order path overhead interface as part of SONET overhead termination functions. Therfore, the user must insert a long enough
delay or use the DTN signal to read/write these registers correctly.
ns
tADSRDTR ADSN or DSN Rise to DTN Rise
—
2.9
13.3
ns
tCSRDT3
CSN Rise to DTN 3-state
—
2.9
13.0
ns
tDTVDV
DTN Valid to DATA Valid
—
0
ns
tADSRD3
ADSN Rise to DATA 3-state
—
2.9
14 + MPCLK§
§ DATA[15:0] is enabled by a retimed version of the ADSN.
ns
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