
Hardware Design Guide, Revision 2
4565B Ultramapper Full Transport Retiming Device
December 17, 2003
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
Agere Systems Inc.
45
Figure 5-16. NSMI Clock and Data Diagram for E13 NSMI Mode 2 (NSMI <--> E13 <--> SPEMPR <--> STM-N)
Table 5-12. NSMI Inputs Specifications
Name
Reference
Edge
Rising/Falling
Max Rise
Time (ns)
Max Fall
Time (ns)
Min Setup
(ns)
Min Hold
(ns)
NSMIRXDATA[3:1]
NSMIRXCLK
R
3.5
5
0
NSMIRXSYNC[3:1]
NSMIRXCLK
R
3.5
5
0
Table 5-13. NSMI Outputs Specifications
Name
Reference
Edge
Rising/Falling
Propagation Delay
Min (ns)
Max (ns)
NSMITXDATA[3:1]
NSMITXCLK
R
0.5
8.75
NSMITXSYNC[3:1]
NSMITXCLK
R
0.5
8.75
RXDATAEN[3:1]
NSMIRXCLK
R
0.5
8.75
TXDATAEN[3:1]
NSMITXCLK
R
0.5
8.75
NSMIRXSYNC[3:1]
NSMIRXCLK
R
0.5
8.75
NSMI_TXDATAEN
(output)
NSMI_TXCLK
(51.84 MHz output)
E3 frame
(for info only)
NSMI_TXDATA
(output)
NSMI_TXSYNC
(output)
NSMI_RXCLK
(51.84 MHz output)
E3 frame
(For info only)
NSMI_RXDATA
(Input)
NSMI_RXSYNC
(output)
NSMI_RXDATAEN
(output)
1536 bits
Position of this pulse is provisionable 0-256 bits before C11
FRAME, RAI, RSVD
C11 = 0
Cj3 = 0
Frame
Stuff = data
1536 bits
Position of this pulse is provisionable 0-256 bits before C11
FRAME, RAI, RSVD
C11 = 0
Cj3 = 0
Frame
Stuff = data
Notes:
Clock from E13 is at 51.84 MHz rate and is not gapped. TXDATAEN is the combination of an internal clock enable and data enable from SPEMPR.
TXDATAEN is used to mark the overhead time and control bits time of the E3 frame. Clock enable is used to gap the clock rate to 34.368 MHz.
C11’s (the first C bit of the first tributary) position is optionally marked by TXSYNC, which is provisioned to be 0 to 255 bits before C11 (bit 385 of the E3
frame).
During periods where the OH is present, the TXDATAEN signal goes low.
All C bits are zero and the stuff bits are used for data.