參數(shù)資料
型號(hào)： 4565B2
廠商： LSI CORP
元件分類： 數(shù)字傳輸電路
英文描述： ATM/SONET/SDH SUPPORT CIRCUIT, PBGA909
封裝： PLASTIC, BGA-909
文件頁數(shù)： 44/61頁
文件大?。?/td> 1691K
代理商： 4565B2
Hardware Design Guide, Revision 2
4565B Ultramapper Full Transport Retiming Device
December 17, 2003
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
Agere Systems Inc.
49
Table 6-5. M13/E13 Input Clocks Specifications
Clock Name
Period
(ns)
Frequency
Accuracy
(ppm)
Jitter
Rise
(ns)
Fall
(ns)
Min/Max
Duty Cycle
DS2AISCLK
158.42
6.312 MHz
30
—
5
Max
50% ± 5%
E2AISCLK
118.37
8.448 MHz
30
—
5
Max
50% ± 5%
Table 6-6. DS3/E3 DJA Input Clocks Specifications
Clock Name
Period
(ns)
Frequency
Accuracy
(ppm)
Jitter
Rise
(ns)
Fall
(ns)
Min/Max
Duty Cycle
DS3XCLK
22.35
44.736 MHz
20
0.01 UIp-p or 0.22 nsp-p
(10 kHz—400 kHz)
3.5
Max
50% ± 5%
E3XCLK
29.09
34.368 MHz
20
0.01 UIp-p or 0.29 nsp-p
(100 kHz—800 kHz)
3.5
Max
50% ± 5%
Table 6-7. LOPOH Input Clock Specifications
Clock Name
Period
(ns)
Frequency
Accuracy
(ppm)
Jitter
Rise
(ns)
Fall
(ns)
Min/Max
Duty Cycle
LOPOHCLKIN
51.44
19.44 MHz
—
8
Max
50% ± 5%
Table 6-8. Microprocessor Interface Input Clocks Specifications
Clock Name
Period
(ns)
Frequency
Accuracy
(ppm)
Jitter
Rise
(ns)
Fall
(ns)
Min/Max
Duty Cycle
MPCLK (min)*
62.5
16 MHz
—
4
Min
50% ± 10%
MPCLK (max)
15.15
66 MHz
—
4
Max
50% ± 10%
* If DTN is used, then the maximum frequency for MPCLK is determined by the processor’s setup specification for DTN. MPU maximum bus oper-
ating frequency = 1/(MPU DTN setup time + tDTNVPD). For example, an 8 ns setup time would limit MPCLK to 50 MHz for reliable DTN detec-
tion.
Table 6-9. Framer PLL Input Clocks Specifications
Clock Name
Period
(ns)
Frequency
Accuracy
(ppm)
Jitter
Rise
(ns)
Fall
(ns)
Min/Max
Duty Cycle
CLKIN_PLL
19.2
51.84 MHz
20
GR-499 and
G.823
—
50% ± 10%
CHIRXGTCLK (DS1 mode) 647.66
1.544 MHz
32
GR-499
10
Max
50% ± 10%
CHIRXGTCLK (E1 mode)
488.28
2.048 MHz
50
G.823
10
Max
50% ± 10%
Table 6-10. CHI Input Clocks Specifications
Clock Name
Period
(ns)
Frequency
Accuracy
(ppm)
Jitter
Rise
(ns)
Fall
(ns)
Min/Max
Duty Cycle
CHIRXGCLK (CHI mode)
488.28
2.048 MHz
50
—
10
Max
50% ± 10%
CHIRXGCLK (CHI mode)
244.14
4.096 MHz
50
—
10
Max
50% ± 10%
CHIRXGCLK (CHI mode)
122.07
8.192 MHz
50
—
10
Max
50% ± 10%
CHIRXGCLK (CHI mode)
61.035
16.384 MHz
50
—
10
Max
50% ± 10%
CHITXGCLK (CHI mode)
488.28
2.048 MHz
50
—
10
Max
50% ± 10%
CHITXGCLK (CHI mode)
244.14
4.096 MHz
50
—
10
Max
50% ± 10%
CHITXGCLK (CHI mode)
122.07
8.192 MHz
50
—
10
Max
50% ± 10%
CHITXGCLK (CHI mode)
61.035
16.384 MHz
50
—
10
Max
50% ± 10%
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