參數(shù)資料
型號(hào)： 4565B2
廠商： LSI CORP
元件分類： 數(shù)字傳輸電路
英文描述： ATM/SONET/SDH SUPPORT CIRCUIT, PBGA909
封裝： PLASTIC, BGA-909
文件頁(yè)數(shù)： 31/61頁(yè)
文件大?。?/td> 1691K
代理商： 4565B2
Hardware Design Guide, Revision 2
4565B Ultramapper Full Transport Retiming Device
December 17, 2003
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
Agere Systems Inc.
37
5 Timing
5.1 TMUX High-Speed Interface Timing
Figure 5-1. TMUX LVDS Signal Rise/Fall Timing
Figure 5-2. TMUX LVDS Clock and Data Timing
Table 5-1. High-Speed Interface Inputs Specifications
Name
Reference
Edge
Rising/Falling
Max Rise
Time (ns)
Max Fall
Time (ns)
Min Setup
(ns)
Min Hold
(ns)
RHSDP/N (622 MHz)*
* Input serial data stream should have minimum eye opening of 0.4 UIp-p, and no more than 60 consecutive bits that have no transitional edge
within one minute. It must meet 100 ps maximum phase variation limit over a 200 ns interval; this translates to a frequency change of 500 ppm.
Asynchronous
—
0.5
—
RHSDP/N (155 MHz)